?? dsp28_swprioritizedisrlevels.h
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//
// TMDX BETA RELEASE
// Intended for product evaluation purposes
//
//###########################################################################
//
// FILE: DSP28_SWPrioritizedIsrLevels.h
//
// TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine
// Level definitions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.1 | 30 Jan 2002 | A.T. | Original Release
//###########################################################################
#ifndef DSP28_SW_PRIORITZIED_ISR_H
#define DSP28_SW_PRIORITZIED_ISR_H
//-------------------------------------------------------------------------------
// Interrupt Enable Register Allocation For F2810/12 Devices:
//-------------------------------------------------------------------------------
// Interrupts can be enabled/disabled using the CPU interrupt enable register
// (IER) and the PIE interrupt enable registers (PIIER1 to PIEIER12). The table
// below lists the allocation of the various interrupts to these registers:
//
//-----------------------------------------------------------------------------------
// CPU | PIEIER1 to PIEIER12 |
// IER | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
// =====|=========|=========|=========|=========|=========|=========|=======|=======|
// INT1 |PDPINTA |PDPINTB | resvd | XINT1 | XINT2 |ADCINT | TINT0 |WAKEINT|
// | (EV-A) | (EV-B) | | | | | | |
// INT2 |CMP1INT |CMP2INT |CMP3INT |T1PINT |T1CINT |T1UFINT |T1OFINT| resvd |
// | (EV-A) | (EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) | |
// INT3 |T2PINT |T2CINT |T2UFINT |T2OFINT |CAPINT1 |CAPINT2 |CAPINT3| resvd |
// | (EV-A) | (EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) |(EV-A) | |
// INT4 |CMP4INT |CMP5INT |CMP6INT |T3PINT |T3CINT |T3UFINT |T3OFINT| resvd |
// | (EV-B) | (EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) | |
// INT5 |T4PINT |T4CINT |T4UFINT |T4OFINT |CAPINT4 |CAPINT5 |CAPINT6| resvd |
// | (EV-B) | (EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) |(EV-B) | |
// INT6 |SPIRXINTA|SPITXINTA| resvd | resvd | MRINTA | MXINTA | resvd | resvd |
// | (SPI-A) | (SPI-A) | | |(McBSP-A)|(McBSP-A)| | |
// INT7 | resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
// INT8 | resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
// INT9 |SCIRXINTA|SCITXINTA|SCIRXINTB|SCITXINTB|ECAN0INTA|ECAN1INTA| resvd | resvd |
// | (SCI-A) | (SCI-A) |(SCI-B) |(SCI-B) |(ECAN-A) |(ECAN-A) | | |
// INT10| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
// INT11| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
// INT12| resvd | resvd | resvd | resvd | resvd | resvd | resvd | resvd |
//-------------------------------------------------------------------------------
// INT13| INT13
// INT14| INT14
// INT15| DATALOG
// INT16| RTOSINT
//-------------------------------------------------------------------------------
//
//-------------------------------------------------------------------------------
// Set "Global" Interrupt Priority Level (IER register):
//-------------------------------------------------------------------------------
// The user must set the appropriate priority level for each of the CPU
// interrupts. This is termed as the "global" priority. The priority level
// must be a number between 1 (highest) to 16 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used. This
// will also reduce code size by not including ISR's that are not used.
//
// Note: The priority levels below are used to calculate the IER register
// interrupt masks MINT1 to MINT16.
//
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 16 = lowest priority
#define INT1PL 2 // Group1 Interrupts (PIEIER1)
#define INT2PL 1 // Group2 Interrupts (PIEIER2)
#define INT3PL 4 // Group3 Interrupts (PIEIER3)
#define INT4PL 2 // Group4 Interrupts (PIEIER4)
#define INT5PL 2 // Group5 Interrupts (PIEIER5)
#define INT6PL 3 // Group6 Interrupts (PIEIER6)
#define INT7PL 0 // reserved
#define INT8PL 0 // reserved
#define INT9PL 3 // Group9 Interrupts (PIEIER9)
#define INT10PL 0 // reserved
#define INT11PL 0 // reserved
#define INT12PL 0 // reserved
#define INT13PL 4 // XINT3
#define INT14PL 4 // INT14 (TINT2)
#define INT15PL 4 // DATALOG
#define INT16PL 4 // RTOSINT
//-------------------------------------------------------------------------------
// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers):
//-------------------------------------------------------------------------------
// The user must set the appropriate priority level for each of the PIE
// interrupts. This is termed as the "group" priority. The priority level
// must be a number between 1 (highest) to 8 (lowest). A value of 0 must
// be entered for reserved interrupts or interrupts that are not used. This
// will also reduce code size by not including ISR's that are not used:
//
// Note: The priority levels below are used to calculate the following
// PIEIER register interrupt masks:
// MG11 to MG18
// MG21 to MG28
// MG31 to MG38
// MG41 to MG48
// MG51 to MG58
// MG61 to MG68
// MG71 to MG78
// MG81 to MG88
// MG91 to MG98
// MG101 to MG108
// MG111 to MG118
// MG121 to MG128
//
// Note: The priority levels shown here may not make sense in a
// real application. This is for demonstration purposes only!!!
//
// The user should change these to values that make sense for
// their application.
//
// 0 = not used
// 1 = highest priority
// ...
// 8 = lowest priority
//
#define G11PL 7 // PDPINTA (EV-A)
#define G12PL 6 // PDPINTB (EV-B)
#define G13PL 0 // reserved
#define G14PL 1 // XINT1 (External)
#define G15PL 3 // XINT2 (External)
#define G16PL 2 // ADCINT (ADC)
#define G17PL 1 // TINT0 (CPU Timer 0)
#define G18PL 5 // WAKEINT (WD/LPM)
#define G21PL 4 // CMP1INT (EV-A)
#define G22PL 3 // CMP2INT (EV-A)
#define G23PL 2 // CMP3INT (EV-A)
#define G24PL 1 // T1PINT (EV-A)
#define G25PL 5 // T1CINT (EV-A)
#define G26PL 6 // T1UFINT (EV-A)
#define G27PL 7 // T1OFINT (EV-A)
#define G28PL 0 // reserved
#define G31PL 4 // T2PINT (EV-A)
#define G32PL 1 // T2CINT (EV-A)
#define G33PL 1 // T2UFINT (EV-A)
#define G34PL 2 // T2OFINT (EV-A)
#define G35PL 2 // CAPINT1 (EV-A)
#define G36PL 1 // CAPINT2 (EV-A)
#define G37PL 3 // CAPINT3 (EV-A)
#define G38PL 0 // reserved
#define G41PL 2 // CMP4INT (EV-B)
#define G42PL 1 // CMP5INT (EV-B)
#define G43PL 3 // CMP6INT (EV-B)
#define G44PL 3 // T3PINT (EV-B)
#define G45PL 2 // T3CINT (EV-B)
#define G46PL 2 // T3UFINT (EV-B)
#define G47PL 1 // T3OFINT (EV-B)
#define G48PL 0 // reserved
#define G51PL 1 // T4PINT (EV-B)
#define G52PL 7 // T4CINT (EV-B)
#define G53PL 2 // T4UFINT (EV-B)
#define G54PL 6 // T4OFINT (EV-B)
#define G55PL 5 // CAPINT4 (EV-B)
#define G56PL 6 // CAPINT5 (EV-B)
#define G57PL 7 // CAPINT6 (EV-B)
#define G58PL 0 // reserved
#define G61PL 3 // SPIRXINTA (SPI-A)
#define G62PL 1 // SPITXINTA (SPI-A)
#define G63PL 0 // reserved
#define G64PL 0 // reserved
#define G65PL 2 // MRINTA (McBSP-A)
#define G66PL 1 // MXINTA (McBSP-A)
#define G67PL 0 // reserved
#define G68PL 0 // reserved
#define G71PL 0 // reserved
#define G72PL 0 // reserved
#define G73PL 0 // reserved
#define G74PL 0 // reserved
#define G75PL 0 // reserved
#define G76PL 0 // reserved
#define G77PL 0 // reserved
#define G78PL 0 // reserved
#define G81PL 0 // reserved
#define G82PL 0 // reserved
#define G83PL 0 // reserved
#define G84PL 0 // reserved
#define G85PL 0 // reserved
#define G86PL 0 // reserved
#define G87PL 0 // reserved
#define G88PL 0 // reserved
#define G91PL 1 // SCIRXINTA (SCI-A)
#define G92PL 5 // SCITXINTA (SCI-A)
#define G93PL 3 // SCIRXINTB (SCI-B)
#define G94PL 4 // SCITXINTB (SCI-B)
#define G95PL 1 // ECAN0INTA (ECAN-A)
#define G96PL 1 // ECAN1INTA (ECAN-A)
#define G97PL 0 // reserved
#define G98PL 0 // reserved
#define G101PL 0 // reserved
#define G102PL 0 // reserved
#define G103PL 0 // reserved
#define G104PL 0 // reserved
#define G105PL 0 // reserved
#define G106PL 0 // reserved
#define G107PL 0 // reserved
#define G108PL 0 // reserved
#define G111PL 0 // reserved
#define G112PL 0 // reserved
#define G113PL 0 // reserved
#define G114PL 0 // reserved
#define G115PL 0 // reserved
#define G116PL 0 // reserved
#define G117PL 0 // reserved
#define G118PL 0 // reserved
#define G121PL 0 // reserved
#define G122PL 0 // reserved
#define G123PL 0 // reserved
#define G124PL 0 // reserved
#define G125PL 0 // reserved
#define G126PL 0 // reserved
#define G127PL 0 // reserved
#define G128PL 0 // reserved
// There should be no need to modify code below this line
//-------------------------------------------------------------------------------
// Automatically generate IER interrupt masks MINT1 to MINT16:
//
// Beginning of MINT1:
#if (INT1PL == 0)
#define MINT1_1PL ~(1 << 0)
#else
#define MINT1_1PL 0xFFFF
#endif
#if (INT2PL >= INT1PL) || (INT2PL == 0)
#define MINT1_2PL ~(1 << 1)
#else
#define MINT1_2PL 0xFFFF
#endif
#if (INT3PL >= INT1PL) || (INT3PL == 0)
#define MINT1_3PL ~(1 << 2)
#else
#define MINT1_3PL 0xFFFF
#endif
#if (INT4PL >= INT1PL) || (INT4PL == 0)
#define MINT1_4PL ~(1 << 3)
#else
#define MINT1_4PL 0xFFFF
#endif
#if (INT5PL >= INT1PL) || (INT5PL == 0)
#define MINT1_5PL ~(1 << 4)
#else
#define MINT1_5PL 0xFFFF
#endif
#if (INT6PL >= INT1PL) || (INT6PL == 0)
#define MINT1_6PL ~(1 << 5)
#else
#define MINT1_6PL 0xFFFF
#endif
#if (INT7PL >= INT1PL) || (INT7PL == 0)
#define MINT1_7PL ~(1 << 6)
#else
#define MINT1_7PL 0xFFFF
#endif
#if (INT8PL >= INT1PL) || (INT8PL == 0)
#define MINT1_8PL ~(1 << 7)
#else
#define MINT1_8PL 0xFFFF
#endif
#if (INT9PL >= INT1PL) || (INT9PL == 0)
#define MINT1_9PL ~(1 << 8)
#else
#define MINT1_9PL 0xFFFF
#endif
#if (INT10PL >= INT1PL) || (INT10PL == 0)
#define MINT1_10PL ~(1 << 9)
#else
#define MINT1_10PL 0xFFFF
#endif
#if (INT11PL >= INT1PL) || (INT11PL == 0)
#define MINT1_11PL ~(1 << 10)
#else
#define MINT1_11PL 0xFFFF
#endif
#if (INT12PL >= INT1PL) || (INT12PL == 0)
#define MINT1_12PL ~(1 << 11)
#else
#define MINT1_12PL 0xFFFF
#endif
#if (INT13PL >= INT1PL) || (INT13PL == 0)
#define MINT1_13PL ~(1 << 12)
#else
#define MINT1_13PL 0xFFFF
#endif
#if (INT14PL >= INT1PL) || (INT14PL == 0)
#define MINT1_14PL ~(1 << 13)
#else
#define MINT1_14PL 0xFFFF
#endif
#if (INT15PL >= INT1PL) || (INT15PL == 0)
#define MINT1_15PL ~(1 << 14)
#else
#define MINT1_15PL 0xFFFF
#endif
#if (INT16PL >= INT1PL) || (INT16PL == 0)
#define MINT1_16PL ~(1 << 15)
#else
#define MINT1_16PL 0xFFFF
#endif
#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \
MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \
MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \
MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL)
// End Of MINT1.
// Beginning of MINT2:
#if (INT1PL >= INT2PL) || (INT1PL == 0)
#define MINT2_1PL ~(1 << 0)
#else
#define MINT2_1PL 0xFFFF
#endif
#if (INT2PL == 0)
#define MINT2_2PL ~(1 << 1)
#else
#define MINT2_2PL 0xFFFF
#endif
#if (INT3PL >= INT2PL) || (INT3PL == 0)
#define MINT2_3PL ~(1 << 2)
#else
#define MINT2_3PL 0xFFFF
#endif
#if (INT4PL >= INT2PL) || (INT4PL == 0)
#define MINT2_4PL ~(1 << 3)
#else
#define MINT2_4PL 0xFFFF
#endif
#if (INT5PL >= INT2PL) || (INT5PL == 0)
#define MINT2_5PL ~(1 << 4)
#else
#define MINT2_5PL 0xFFFF
#endif
#if (INT6PL >= INT2PL) || (INT6PL == 0)
#define MINT2_6PL ~(1 << 5)
#else
#define MINT2_6PL 0xFFFF
#endif
#if (INT7PL >= INT2PL) || (INT7PL == 0)
#define MINT2_7PL ~(1 << 6)
#else
#define MINT2_7PL 0xFFFF
#endif
#if (INT8PL >= INT2PL) || (INT8PL == 0)
#define MINT2_8PL ~(1 << 7)
#else
#define MINT2_8PL 0xFFFF
#endif
#if (INT9PL >= INT2PL) || (INT9PL == 0)
#define MINT2_9PL ~(1 << 8)
#else
#define MINT2_9PL 0xFFFF
#endif
#if (INT10PL >= INT2PL) || (INT10PL == 0)
#define MINT2_10PL ~(1 << 9)
#else
#define MINT2_10PL 0xFFFF
#endif
#if (INT11PL >= INT2PL) || (INT11PL == 0)
#define MINT2_11PL ~(1 << 10)
#else
#define MINT2_11PL 0xFFFF
#endif
#if (INT12PL >= INT2PL) || (INT12PL == 0)
#define MINT2_12PL ~(1 << 11)
#else
#define MINT2_12PL 0xFFFF
#endif
#if (INT13PL >= INT2PL) || (INT13PL == 0)
#define MINT2_13PL ~(1 << 12)
#else
#define MINT2_13PL 0xFFFF
#endif
#if (INT14PL >= INT2PL) || (INT14PL == 0)
#define MINT2_14PL ~(1 << 13)
#else
#define MINT2_14PL 0xFFFF
#endif
#if (INT15PL >= INT2PL) || (INT15PL == 0)
#define MINT2_15PL ~(1 << 14)
#else
#define MINT2_15PL 0xFFFF
#endif
#if (INT16PL >= INT2PL) || (INT16PL == 0)
#define MINT2_16PL ~(1 << 15)
#else
#define MINT2_16PL 0xFFFF
#endif
#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \
MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \
MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \
MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL)
// End Of MINT2.
// Beginning of MINT3:
#if (INT1PL >= INT3PL) || (INT1PL == 0)
#define MINT3_1PL ~(1 << 0)
#else
#define MINT3_1PL 0xFFFF
#endif
#if (INT2PL >= INT3PL) || (INT2PL == 0)
#define MINT3_2PL ~(1 << 1)
#else
#define MINT3_2PL 0xFFFF
#endif
#if (INT3PL == 0)
#define MINT3_3PL ~(1 << 2)
#else
#define MINT3_3PL 0xFFFF
#endif
#if (INT4PL >= INT3PL) || (INT4PL == 0)
#define MINT3_4PL ~(1 << 3)
#else
#define MINT3_4PL 0xFFFF
#endif
#if (INT5PL >= INT3PL) || (INT5PL == 0)
#define MINT3_5PL ~(1 << 4)
#else
#define MINT3_5PL 0xFFFF
#endif
#if (INT6PL >= INT3PL) || (INT6PL == 0)
#define MINT3_6PL ~(1 << 5)
#else
#define MINT3_6PL 0xFFFF
#endif
#if (INT7PL >= INT3PL) || (INT7PL == 0)
#define MINT3_7PL ~(1 << 6)
#else
#define MINT3_7PL 0xFFFF
#endif
#if (INT8PL >= INT3PL) || (INT8PL == 0)
#define MINT3_8PL ~(1 << 7)
#else
#define MINT3_8PL 0xFFFF
#endif
#if (INT9PL >= INT3PL) || (INT9PL == 0)
#define MINT3_9PL ~(1 << 8)
#else
#define MINT3_9PL 0xFFFF
#endif
#if (INT10PL >= INT3PL) || (INT10PL == 0)
#define MINT3_10PL ~(1 << 9)
#else
#define MINT3_10PL 0xFFFF
#endif
#if (INT11PL >= INT3PL) || (INT11PL == 0)
#define MINT3_11PL ~(1 << 10)
#else
#define MINT3_11PL 0xFFFF
#endif
#if (INT12PL >= INT3PL) || (INT12PL == 0)
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