/*-----------------------------------------------------------------------------				
*
* File:  sar.h
*
* Description:  
*
*     Constants and Definitions for 860SAR sample code. [Interrupt-
*     driven version].
*
* History:
*
* April 1998  jes 	Created Transparent Version from HDLC version
*---------------------------------------------------------------------------*/

#ifndef SAR_H
#define SAR_H

/*-------------------------------------------------------------------------*/
/*                     MPC8xx CONSTANTS AND DEFINITIONS                    */
/*-------------------------------------------------------------------------*/

#define INTERRUPT_LEVEL 4 	/* integer between 0 and 7 inclusive */

#define BASE_EVT 0x0  /* Base Address of Exception Vector Table */

#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  /* Base address of 
												external interrupt 
												code               */

#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)


/* ==================== APPLICATION CONSTANTS AND DEFINITIONS  =============== */


typedef struct bcsr 

{
	UWORD  bcsr0; /* Board Control and Status Register */
	UWORD  bcsr1;
	UWORD  bcsr2;
	UWORD  bcsr3;

} BCSR;


typedef struct BufferDescriptor 

{
   UHWORD bd_cstatus;     /* control and status */
   UHWORD bd_length;      /* transfer length */
   UBYTE  *bd_addr;       /* buffer address */

} BD;

#define BD_RX_ERROR 0x93    /* Mask for set of Receive Buffer Errors,
                               including: HEC, ABT, LN, CR */


/*--------------------------------------------------------------*/
/* SAR Exception Queue Entry Bit Definitions                    */
/*--------------------------------------------------------------*/

#define RXB	0x10000		/* Rcv Buffer event    */
#define TXB 	0x20000		/* Xmit bufffer event  */
#define BSY	0x40000		/* Receiver busy event */
#define RXF	0x80000		/* Received frame event */
#define UN 	0x100000	/* Xmit Underrun event */
#define APCO	0x800000	/* APC Overflow event  */
#define CNG	0x10000000	/* Congestion event    */

#define Q_ENTRY_VALID 0x80000000 /* Interrupt Queue entry valid bit */
#define Q_WRAP        0x40000000 /* Interrupt Queue entry wrap bit  */

/*-----------------------------------------------------------------*/
/* Number of Instructions in Vector Table for particular Interrupt */
/*-----------------------------------------------------------------*/

#define VECTOR_BLOCK_LEN 0x100

/*------------------------------------*/
/* SIU Vector Interrupt Code: Level 4 */
/*------------------------------------*/

#define IC_LEVEL_4  0x24

/*----------------------------------------------------------*/
/* SCCx Interrupt Vector Code in CPM Vector Register (CIVR) */
/*----------------------------------------------------------*/

#define SCC1_VECTOR 0x1E
#define SCC2_VECTOR 0x1D
#define SCC3_VECTOR 0x1C
#define SCC4_VECTOR 0x1B

#define	ETHEN	0x20000000	  /* ETHEN in bit 2 of BCSR1 */

#define READY_TO_RX_CMD  0   /* Ready to receive a command */


#define NUM_FRAMES	2	/* Number of Frames to Transmit */
#define FRAME_LENGTH	96      /* Length of each frame (bytes) */

#define RAW_CELL_BUFF_SIZE 64	/* Raw cell buffer size (bytes) */


/*----------------------------------------------------------*/
/* SAR Data structure definitions.                          */
/*----------------------------------------------------------*/

#define CMD_FLAG 0x0001

/* Buffer Descriptor */ 

typedef _Packed struct 
{
    UHWORD  status; 	 /* Transmit BD status/control field */
    UHWORD  length;	 /* Length of frame to transmit */ 
    UBYTE   *buf;	 /* Pointer to frame data structure */ 
    UHWORD  cpcs_uu_cpi; /* CPCS, UU, anc CPI fields in PDU */ 
    UBYTE   reserved[2];
}BD_860SAR;

typedef _Packed struct
{
    /* RCT */
    UHWORD  r_status ;
    UHWORD  rbalen ;
    UWORD   rcrc;
    void    *rb_ptr;
    UHWORD  rtmlen;
    UHWORD  rbd_ptr;
    UHWORD  rbase;
    UHWORD  tstamp;
    UHWORD  imask;

    /* Reserved Space */
    UBYTE   RESERVED0[10];

    /* TCT */
    UHWORD  t_status ;
    UHWORD  tbalen ;
    UWORD   tcrc;
    void    *tb_ptr;
    UHWORD  ttmlen ;
    UHWORD  tbd_ptr;
    UHWORD  tbase;
    UHWORD  reserved;
    UWORD   chead;
    UHWORD  apcl;
    UHWORD  apcpr;
    UHWORD  apcp;
    UHWORD  apcpf;
}Ct ;

#define  CT_SIZE 0x40  	/* Connection table size = 64 bytes */ 

typedef _Packed struct
{
    VUHWORD apct_base1;     /* APC Table - First Priority Base pointer */
    VUHWORD apct_end1;     /* First APC Table - Length */
    VUHWORD apct_ptr1;     /* First APC Table Pointer */
    VUHWORD apct_sptr1;     /* APC Table First Priority Service pointer */
    VUBYTE  RESERVRD0[0x8];     /* reserved */
    VUHWORD apc_mi;     /* APC - Max Iteration */
    VUHWORD ncist;     /* Number of Cells In Slot Time */
    VUHWORD apcnt;     /* APC - N Timer */
    VUBYTE  RESERVRD1[0xa];     /* reserved */
    VUHWORD apct_base2;     /* APC Table - Second Priority Base pointer */
    VUHWORD apct_end2;     /* Second APC Table - Length */
    VUHWORD apct_ptr2;     /* Second APC Table Pointer */
    VUHWORD apct_sptr2;     /* APC Table Second Priority Service pointer */
    VUBYTE  RESERVRD2[0x18];     /* reserved */
}APC_PARAMETER_TABLE_PL2;

/*
 * ATM Cell data structure used in TCT.  Note HEC is 
 * not included in the structue because it is automatically 
 * inserted by the SAR.
 *
 * Note: The structure is layed out as such to adhere to the 
 * transmit sequence (i.e. GFC first, followed by VPI, etc).
 *
*/ 

typedef _Packed struct
{
 unsigned clp:1; 	/* Cell Loss Priority         */
 unsigned pti:3; 	/* Payload type Identifier    */
 unsigned vci:16;	/* Virtual Channel Identifier */ 
 unsigned vpi:8;	/* Virtual Path Identifier    */ 
 unsigned gfc:4; 	/* Generic Flow Control;      */ 
}Cell_header_xmit; 

typedef _Packed struct
{
 unsigned gfc:4; 	/* Generic Flow Control;      */ 
 unsigned vpi:8;	/* Virtual Path Identifier    */ 
 unsigned vci:16;	/* Virtual Channel Identifier */ 
 unsigned pti:3; 	/* Payload type Identifier    */
 unsigned clp:1; 	/* Cell Loss Priority         */
}Cell_header_rcv; 

/*----------------------------------------------------------*/
/* Memory Address and Offset Definitions.  Before modifying */
/* keep in mind that some addresses have boundary re-       */
/* quirements.  All offsets are from DPR unless otherwise   */
/* specified.                                               */
/*----------------------------------------------------------*/

#define INT_QUEUE_ADDR 0x320000		/* Interrupt queue Addr */
#define NUM_QUEUE_ENTRIES 0x100		/* Number of queue entries */

#define EXT_CT_ADDR 0x330000		/* External CT Address */

#define TBD_ADDR 0x340000		/* Xmit BD address 256K */
#define RBD_ADDR 0x380000		/* Rcv BD address  256K */
#define RAW_RBD_ADDR 0x380100		/* Rcv raw cell BD addr */
#define RX_BUFF_ADDR 0x3c0000		/* Rcv buffer address   */
#define TX_BUFF_ADDR 0x3c2000		/* Xmit buffer address  */

#define RAW_CELL_RX_BUFF_ADDR 0x3c4000
#define NUM_RAW_CELL_BUFFS 20

#define CT_BASE_OFFSET	0x180	/* Connection Table */ 
#define AP_BASE_OFFSET  0x124   /* Address Pointer Table base */
#define AM_BASE_OFFSET  0xd0	/* Address Match Table base */
#define AM_END_OFFSET  0xcc	/* Address Match Table end  */

#define XMIT_Q_BASE_OFFSET 0x990 /* Xmit Queue Start */
#define XMIT_Q_END_OFFSET  0x9ce /* Xmit Queue End   */

#define APC_PARAM_OFFSET 0x9e0  /* Start of APC Parameters */
#define APC_BASE_OFFSET  0xad0	/* Start of APC Table */
#define APC_END_OFFSET   0xb50	/* End of APC Table */

#endif