?? csr_1int.lis
字號:
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 REG_RESTORE PRV_PP
0000 ENDIF
0001 CSR_1_CTR_START_BIT: equ 0x01 ; CTR Control register start bit
0001 CSR_1_PWM_START_BIT: equ 0x01 ; PWM Control register start bit
0001 CSR_1_CMP_START_BIT: equ 0x01 ; CMP CR2 register start bit
00E1 CSR_1_SCAN_INT_REG: equ 0x0e1
0001 CSR_1_SCAN_INT_MASK: equ 0x01
0000
0001 CSR_1_Method: equ 1
0000 CSR_1_Method_Freq: equ 0
0001 CSR_1_Method_Period: equ 1
0000
0000 ;--------------------------------------------------
0000 ; Constants for CSR_1 API's
0000 ;--------------------------------------------------
0001 CSR_1_SCAN_CONTINUOUS: equ 0x01
0000 CSR_1_SCAN_ONCE: equ 0x00
0000
0010 CSR_1_SCAN_ACTIVE: equ 0x10 ; Set when scanning is active
0020 CSR_1_SCAN_SET_COMPLETE: equ 0x20 ; Set each time a set of keys is scanned.
0000
0007 CSR_1_ButtonCount: equ 0x7
0000 CSR_1_SliderCount: equ 0x0
0007 CSR_1_TotalSwitchCount: equ 0x7
0000
0000 CSR_1_DAC_LOW: equ 0x00
0001 CSR_1_DAC_HIGH: equ 0x01
0000
0000 CSR_1_ESD_DETECTION: equ 0x0
0007 CSR_1_BUTTONS_EXIST: equ 0x7
0000 CSR_1_SLIDERS_EXIST: equ 0x0
0000
0000 ;--------------------------------------------------
0000 ; Registers Address Constants for CSR_1
0000 ;--------------------------------------------------
0000
0020 CSR_1_PWM_FUNC_REG: equ 0x20 ; PWM Function Reg
0021 CSR_1_PWM_IN_REG: equ 0x21 ; PWM Input Reg
0022 CSR_1_PWM_OUT_REG: equ 0x22 ; PWM Output Reg
0020 CSR_1_PWM_COUNTER_REG: equ 0x20 ; PWM Counter Reg
0021 CSR_1_PWM_PERIOD_REG: equ 0x21 ; PWM Period Reg
0022 CSR_1_PWM_COMPARE_REG: equ 0x22 ; PWM Compare Reg
0023 CSR_1_PWM_CONTROL_REG: equ 0x23 ; PWM Control Reg
0000
0072 CSR_1_ACE_CONTROL1_REG: equ 0x72 ; PWM Function Register
0073 CSR_1_ACE_CONTROL2_REG: equ 0x73 ; PWM Function Register
0000
0024 CSR_1_CTR_COUNTER_LSB_REG: equ 0x24 ; CTR LSB Counter Reg
0025 CSR_1_CTR_PERIOD_LSB_REG: equ 0x25 ; CTR LSB Period Reg
0026 CSR_1_CTR_COMPARE_LSB_REG: equ 0x26 ; CTR LSB Compare Reg
0027 CSR_1_CTR_CONTROL_LSB_REG: equ 0x27 ; CTR LSB Control Reg
0024 CSR_1_CTR_FUNC_LSB_REG: equ 0x24 ; CTR LSB Function Reg
0025 CSR_1_CTR_INPUT_LSB_REG: equ 0x25 ; CTR LSB Input Reg
0026 CSR_1_CTR_OUTPUT_LSB_REG: equ 0x26 ; CTR LSB Output Reg
0000
0028 CSR_1_CTR_COUNTER_MSB_REG: equ 0x28 ; CTR MSB Counter Reg
0029 CSR_1_CTR_PERIOD_MSB_REG: equ 0x29 ; CTR MSB Period Reg
002A CSR_1_CTR_COMPARE_MSB_REG: equ 0x2a ; CTR MSB Compare Reg
002B CSR_1_CTR_CONTROL_MSB_REG: equ 0x2b ; CTR MSB Control Reg
0028 CSR_1_CTR_FUNC_MSB_REG: equ 0x28 ; CTR MSB Function Reg
0029 CSR_1_CTR_INPUT_MSB_REG: equ 0x29 ; CTR MSB Input Reg
002A CSR_1_CTR_OUTPUT_MSB_REG: equ 0x2a ; CTR MSB Output Reg
0000
0000
0000 DR_OFFSET: equ 0x00
0000 DM0_OFFSET: equ 0x00 ; Bank 1
0001 DM1_OFFSET: equ 0x01 ; Bank 1
0003 DM2_OFFSET: equ 0x03 ; Bank 0
00D8 MUX_OFFSET: equ MUX_CR0 ; Bank 1
0000
0000 ;--------------------------------------------------
0000 ; CSR_1 Macro 'Functions'
0000 ;--------------------------------------------------
0000
0000 macro CSR_1_Start_M
0000 or reg[CSR_1_CTR_CONTROL_LSB_REG], CSR_1_CTR_START_BIT
0000 or reg[CSR_1_PWM_CONTROL_REG], CSR_1_PWM_START_BIT
0000 macro CSR_1_Start_Counter_M
0000 or reg[CSR_1_CTR_CONTROL_LSB_REG], CSR_1_CTR_START_BIT
0000 macro CSR_1_Start_CMP_M
0000 mov reg[CSR_1_ACE_CONTROL2_REG], CSR_1_CMP_START_BIT
0000 macro CSR_1_Stop_M
0000 and reg[CSR_1_PWM_CONTROL_REG], ~CSR_1_PWM_START_BIT
0000 and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0000 macro CSR_1_Stop_Counter_M
0000 and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0000 macro CSR_1_Stop_CMP_M
0000 mov reg[CSR_1_ACE_CONTROL2_REG], ~CSR_1_CMP_START_BIT
0000 macro CSR_1_EnableInt_M
0000 M8C_EnableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
0000 macro CSR_1_DisableInt_M
0000 M8C_DisableIntMask CSR_1_SCAN_INT_REG, CSR_1_SCAN_INT_MASK
0000 MSB: equ 0
0001 LSB: equ 1
0000 ;-----------------------------------------------
0000 ; Global Symbols
0000 ;-----------------------------------------------
0000
export _CSR_1_SCAN_ISR
;-----------------------------------------------------------------------------
; FUNCTION NAME: CSR_1_CAPTURE_ISR
;
; DESCRIPTION:
; Interrupt Service Routine for the 16 bit counter in the CSR. If the interrupt
; is enabled and the comparator trips or the counter reaches terminal count (as
; selected by user parameter) the code execution will vector to this ISR.
;
;-----------------------------------------------------------------------------
;
;
0000 _CSR_1_SCAN_ISR:
0000
0000 6273FE mov reg[CSR_1_ACE_CONTROL2_REG], ~CSR_1_CMP_START_BIT
0003 4123FE and reg[CSR_1_PWM_CONTROL_REG], ~CSR_1_PWM_START_BIT
0006 4127FE and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0009 08 push A
000A 10 push X
000B
000B 5100 mov A, [CSR_1_bSwitchNum] ; Get Counter Counter value
000D 64 asl A
000E 5C mov X,A
000F
000F 5D24 mov A, reg[CSR_1_CTR_COUNTER_LSB_REG] ; Dummy Read
0011 5D26 mov A, reg[CSR_1_CTR_COMPARE_LSB_REG] ; Get Counter LSB
0013 5401 mov [X+(CSR_1_iaSwResult+LSB)],A
0015
0015 5D28 mov A, reg[CSR_1_CTR_COUNTER_MSB_REG] ; Dummy Read
0017 5D2A mov A, reg[CSR_1_CTR_COMPARE_MSB_REG] ; Get Counter MSB
0019 5400 mov [X+(CSR_1_iaSwResult+MSB)],A
001B
001B ; Reset Counter period to 0xFFFF
001B 6225FF mov reg[CSR_1_CTR_PERIOD_LSB_REG], 0xFF
001E 6229FF mov reg[CSR_1_CTR_PERIOD_MSB_REG], 0xFF
0021
0021 ; Subtract result from 0xFFFF
0021 50FF mov A,0xFF
0023 1301 sub A,[X+(CSR_1_iaSwResult+LSB)]
0025 5401 mov [X+(CSR_1_iaSwResult+LSB)],A
0027 50FF mov A,0xFF
0029 1B00 sbb A,[X+(CSR_1_iaSwResult+MSB)]
002B 5400 mov [X+(CSR_1_iaSwResult+MSB)],A
002D
002D
002D ; Disconnect the switch (place in reset state)
002D 5100 mov A,[CSR_1_bSwitchNum]
002F 7C0000 lcall CSR_1_iGetPortPin ; Get switch port and mask
0032 7C0000 lcall CSR_1_DisableSwitch ; Enable first switch
0035
0035
0035 ; Determine if scanning should continue
0035 ; If still in scan mode select next switch to scan
0035
0035 7600 inc [CSR_1_bSwitchNum] ; Advance to next switch
0037 5100 mov A, [CSR_1_bScanEnd] ; Check to see if it is out of range
0039 3A00 cmp A,[CSR_1_bSwitchNum] ; Move new value to A
003B D00C jnc .KeepScanning ; Not end of scan list yet
003D
003D ; At end of scan list, determine if this is a one time scan or continuous
003D
003D 2E0020 or [CSR_1_bfStatus],CSR_1_SCAN_SET_COMPLETE ; Set Scan complete flag
0040 470001 tst [CSR_1_bfStatus],CSR_1_SCAN_CONTINUOUS ; Continuous scan mode?
0043 A018 jz .STOP_SCANNING ; Stop scanning
0045
0045 .TAKE_IT_FROM_TOP:
0045 5F0000 mov [CSR_1_bSwitchNum],[CSR_1_bScanStart] ; Reset scan at top of list.
0048
0048 .KeepScanning:
0048 5100 mov A, [CSR_1_bPWMPeriod]
004A 6021 mov reg[CSR_1_PWM_PERIOD_REG], A ; Set PWM period
004C
004C 432701 or reg[CSR_1_CTR_CONTROL_LSB_REG], CSR_1_CTR_START_BIT
004F 432301 or reg[CSR_1_PWM_CONTROL_REG], CSR_1_PWM_START_BIT
0052
0052 5100 mov A,[CSR_1_bSwitchNum] ; Enable the next switch
0054 7C0000 lcall CSR_1_iGetPortPin ; Get switch port and mask
0057 7C0000 lcall CSR_1_EnableSwitch ; Enable first switch
005A
005A 8010 jmp .END_SCAN_ISR
005C
005C .STOP_SCANNING:
005C 2600EE and [CSR_1_bfStatus],~(CSR_1_SCAN_ACTIVE|CSR_1_SCAN_CONTINUOUS) ; Clear scan active flag
005F 4123FE and reg[CSR_1_PWM_CONTROL_REG], ~CSR_1_PWM_START_BIT
0062 4127FE and reg[CSR_1_CTR_CONTROL_LSB_REG], ~CSR_1_CTR_START_BIT
0065 6273FE mov reg[CSR_1_ACE_CONTROL2_REG], ~CSR_1_CMP_START_BIT
0068 41E1FE and reg[CSR_1_SCAN_INT_REG], ~CSR_1_SCAN_INT_MASK ; disable specified interrupt enable bit
006B
006B .END_SCAN_ISR:
006B
006B 20 pop X
006C 18 pop A
006D
006D
006D
006D .SCAN_RETURN:
006D ;@PSoC_UserCode_BODY_TERMINAL@ (Do not change this line.)
006D ;---------------------------------------------------
006D ; Insert your custom code below this banner
006D ;---------------------------------------------------
006D ; NOTE: interrupt service routines must preserve
006D ; the values of the A and X CPU registers.
006D
006D ;---------------------------------------------------
006D ; Insert your custom code above this banner
006D ;---------------------------------------------------
006D ;@PSoC_UserCode_END@ (Do not change this line.)
006D
006D 7E reti
006E ; End of File CSR_1INT.asm
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