-------------------------------------------------------------  File: stage.vhd                                      ----  created by Armen Saatchyan : July 09,2001 15:00      ----  mail to khaer@opencores.org                          -------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_ARITH.all;use IEEE.STD_LOGIC_SIGNED.all;entity stage is 	generic (   	iteration : integer range 1 to 24 :=1		);	port (		clk        : in  STD_LOGIC;		x_i       : in  STD_LOGIC_VECTOR (19 downto 0); 		y_i       : in  STD_LOGIC_VECTOR (19 downto 0);		z_i       : in  STD_LOGIC_VECTOR (18 downto 0);		x_out      : out STD_LOGIC_VECTOR (19 downto 0); 		y_out      : out STD_LOGIC_VECTOR (19 downto 0);		z_out      : out STD_LOGIC_VECTOR (18 downto 0);		octant_i  : in  STD_LOGIC_VECTOR (2 downto 0);		octant_out : out STD_LOGIC_VECTOR (2 downto 0)		);	end stage;								   architecture stage of stage is	type TArcTanConst is array (0 to 24) of STD_LOGIC_VECTOR (31 downto 0);	constant ArcTan : TArcTanConst :=(	X"20000000",     --     45                0	X"12E4051D",     --     26,56505118       1	X"09FB385B",     --     14,03624347       2	X"051111D4",     --     7,125016349       3	X"028B0D43",     --     3,576334375       4	X"0145D7E1",     --     1,789910608       5	X"00A2F61E",     --     0,89517371        6	X"00517C55",     --     0,447614171       7	X"0028BE53",     --     0,2238105         8	X"00145F2E",     --     0,111905677       9	X"000A2F98",     --     0,055952892      10	X"000517CC",     --     0,027976453      11	X"00028BE6",     --     0,013988227      12	X"000145F3",     --     0,006994114      13	X"0000A2F9",     --     0,003497057      14	X"0000517C",     --     0,001748528      15	X"000028BE",     --     0,000874264      16	X"0000145F",     --     0,000437132      17	X"00000A2F",     --     0,000218566      18	X"00000517",     --     0,000109283      19	X"0000028B",     --     5,46415E-05      20	X"00000145",     --     2,73208E-05      21	X"000000A2",     --     1,36604E-05      22	X"00000051",     --     6,83019E-06      23	X"00000028"      --     3,41509E-06      24	);	signal		x_in       :   STD_LOGIC_VECTOR (19 downto 0); 	signal	y_in       :  STD_LOGIC_VECTOR (19 downto 0);	signal		z_in       :   STD_LOGIC_VECTOR (18 downto 0);	signal	octant_in  :  STD_LOGIC_VECTOR (2 downto 0);	begin	process (clk)		variable XA   : std_logic_vector (19 downto 0);		variable XB   : std_logic_vector (19 downto 0);		variable XSum : std_logic_vector (19 downto 0);       		variable YA   : std_logic_vector (19 downto 0);		variable YB   : std_logic_vector (19 downto 0);		variable YSum : std_logic_vector (19 downto 0);		variable ZSum : std_logic_vector (18 downto 0);	begin		if clk'event and clk ='1' then	                     			x_in<=x_i;			y_in<=y_i;			z_in<=z_i;			octant_in<=octant_i;			XA := x_in;			XB := sxt(y_in(19 downto iteration),20);----shift_reg						YA := y_in;			YB := ext(x_in(19 downto iteration),20);-----shift_reg						if y_in(19) = '0' 				then 				XSum :=  XA + XB;				YSum :=  YA - YB;   				ZSum := z_in + ArcTan (iteration)(30 downto 12);			else 				XSum := XA - XB;				YSum := YA + YB;   				ZSum := z_in - ArcTan (iteration)(30 downto 12);			end if;			x_out      <= XSum;			y_out      <= YSum;          			z_out      <= ZSum;			octant_out <= octant_in; 		end if;			end process;		end stage;