library verilog;use verilog.vl_types.all;entity mult is    port(        a               : in     vl_logic_vector(15 downto 0);        b               : in     vl_logic_vector(15 downto 0);        \out\           : out    vl_logic_vector(31 downto 0);        clk             : in     vl_logic;        start           : in     vl_logic;        rdy             : out    vl_logic    );end mult;