library verilog;use verilog.vl_types.all;entity boshuxc is    port(        ar1             : in     vl_logic_vector(15 downto 0);        ar2             : in     vl_logic_vector(15 downto 0);        ar3             : in     vl_logic_vector(15 downto 0);        ar4             : in     vl_logic_vector(15 downto 0);        ar5             : in     vl_logic_vector(15 downto 0);        ar6             : in     vl_logic_vector(15 downto 0);        ar7             : in     vl_logic_vector(15 downto 0);        ar8             : in     vl_logic_vector(15 downto 0);        ai1             : in     vl_logic_vector(15 downto 0);        ai2             : in     vl_logic_vector(15 downto 0);        ai3             : in     vl_logic_vector(15 downto 0);        ai4             : in     vl_logic_vector(15 downto 0);        ai5             : in     vl_logic_vector(15 downto 0);        ai6             : in     vl_logic_vector(15 downto 0);        ai7             : in     vl_logic_vector(15 downto 0);        ai8             : in     vl_logic_vector(15 downto 0);        br1             : in     vl_logic_vector(15 downto 0);        br2             : in     vl_logic_vector(15 downto 0);        br3             : in     vl_logic_vector(15 downto 0);        br4             : in     vl_logic_vector(15 downto 0);        br5             : in     vl_logic_vector(15 downto 0);        br6             : in     vl_logic_vector(15 downto 0);        br7             : in     vl_logic_vector(15 downto 0);        br8             : in     vl_logic_vector(15 downto 0);        bi1             : in     vl_logic_vector(15 downto 0);        bi2             : in     vl_logic_vector(15 downto 0);        bi3             : in     vl_logic_vector(15 downto 0);        bi4             : in     vl_logic_vector(15 downto 0);        bi5             : in     vl_logic_vector(15 downto 0);        bi6             : in     vl_logic_vector(15 downto 0);        bi7             : in     vl_logic_vector(15 downto 0);        bi8             : in     vl_logic_vector(15 downto 0);        yr              : out    vl_logic_vector(31 downto 0);        yi              : out    vl_logic_vector(31 downto 0);        clk             : in     vl_logic;        start           : in     vl_logic;        rdy             : out    vl_logic    );end boshuxc;