`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    09:38:03 06/04/07
// Design Name:    
// Module Name:    boshuxc
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//本模塊需要3個CLK.
// 
////////////////////////////////////////////////////////////////////////////////

module boshuxc(ar1,ar2,ar3,ar4,ar5,ar6,ar7,ar8,ai1,ai2,ai3,ai4,ai5,ai6,ai7,ai8,
				br1,br2,br3,br4,br5,br6,br7,br8,bi1,bi2,bi3,bi4,bi5,bi6,bi7,bi8,
				yr,yi,clk,start,rdy);
				
input[15:0] ar1,ar2,ar3,ar4,ar5,ar6,ar7,ar8,ai1,ai2,ai3,ai4,ai5,ai6,ai7,ai8;
input[15:0] br1,br2,br3,br4,br5,br6,br7,br8,bi1,bi2,bi3,bi4,bi5,bi6,bi7,bi8;	//權值
//input[7:0] w1,w2,w3,w4,w5,w6,w7,w8;
input clk,start;
output[31:0] yr,yi;
output rdy;

wire[31:0] war1,war2,war3,war4,war5,war6,war7,war8,wai1,wai2,wai3,wai4,wai5,wai6,wai7,wai8;
wire[31:0] wbr1,wbr2,wbr4,wbr3,wbi1,wbi2,wbi4,wbi3;
wire[31:0] wcr1,wcr2,wci1,wci2;	
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8;
wire rdya;
reg[31:0] yr,yi;
reg rdy=0;	

complexmul mu1(ar1,-ai1,br1,bi1,war1,wai1,clk,start,rdy1);//復數乘法運算
complexmul mu2(ar2,-ai2,br2,bi2,war2,wai2,clk,start,rdy2);
complexmul mu3(ar3,-ai3,br3,bi3,war3,wai3,clk,start,rdy3);
complexmul mu4(ar4,-ai4,br4,bi4,war4,wai4,clk,start,rdy4);
complexmul mu5(ar5,-ai5,br5,bi5,war5,wai5,clk,start,rdy5);
complexmul mu6(ar6,-ai6,br6,bi6,war6,wai6,clk,start,rdy6);
complexmul mu7(ar7,-ai7,br7,bi7,war7,wai7,clk,start,rdy7);
complexmul mu8(ar8,-ai8,br8,bi8,war8,wai8,clk,start,rdy8);

assign rdya=rdy1&&rdy2&&rdy3&&rdy4&&rdy5&&rdy6&&rdy7&&rdy8;

//addm addmodule(war1,war2,war3,war4,war5,war6,war7,war8,wai1,wai2,wai3,wai4,wai5,wai6,wai7,wai8,
//				yr,yi,clk,rdya,rdy);
//實數運算
assign wbr1=war1+war2;
assign wbr2=war3+war4;
assign wbr3=war5+war6;
assign wbr4=war7+war8;

assign wcr1=wbr1+wbr2;
assign wcr2=wbr3+wbr4;



//虛數運算
assign wbi1=wai1+wai2;
assign wbi2=wai3+wai4;
assign wbi3=wai5+wai6;
assign wbi4=wai7+wai8;

assign wci1=wbi1+wbi2;
assign wci2=wbi3+wbi4;

always @ (posedge clk)
begin
	if(rdya)
		begin
			yr<=wcr1+wcr2;
			yi<=wci1+wci2;
			rdy<=1;
		end
	else
		begin
			yr<=32'b0;
			yi<=32'b0;
			rdy<=0;
		end
end

/*

//輸出結果（實數部分）
assign yr=wcr1+wcr2;
//輸出結果（虛數部分）
assign yi=wci1+wci2;		 */
								
endmodule