`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    21:12:11 06/03/07
// Design Name:    
// Module Name:    foremode
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//本模塊為求權值及其前面的模塊綜合	
// 
////////////////////////////////////////////////////////////////////////////////
module foremode(wt0r,wt0i,wt1r,wt1i,wt2r,wt2i,wt3r,wt3i,wt4r,wt4i,wt5r,wt5i,wt6r,wt6i,wt7r,wt7i,clk,rdy);
input clk;
output[15:0] wt0r,wt0i,wt1r,wt1i,wt2r,wt2i,wt3r,wt3i,wt4r,wt4i,wt5r,wt5i,wt6r,wt6i,wt7r,wt7i;//輸出最終權值
output rdy;






endmodule