library verilog;use verilog.vl_types.all;entity jiewei is    port(        ar              : in     vl_logic_vector(31 downto 0);        ai              : in     vl_logic_vector(31 downto 0);        qr              : out    vl_logic_vector(15 downto 0);        qi              : out    vl_logic_vector(15 downto 0);        clk             : in     vl_logic;        start           : in     vl_logic;        rdy             : out    vl_logic    );end jiewei;