Release 7.1.03i - xst H.41Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.81 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.81 s | Elapsed : 0.00 / 0.00 s --> Reading design: jiewei.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "jiewei.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "jiewei"Output Format                      : NGCTarget Device                      : xc3s400-5-pq208---- Source OptionsTop Module Name                    : jieweiAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : jiewei.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "jiewei.v"Module <jiewei> compiledNo errors in compilationAnalysis of file <"jiewei.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <jiewei>.Module <jiewei> is correct for synthesis.     Set property "resynthesize = true" for unit <jiewei>.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <jiewei>.    Related source file is "jiewei.v".WARNING:Xst:647 - Input <ai<9:0>> is never used.WARNING:Xst:647 - Input <ar<9:0>> is never used.WARNING:Xst:1780 - Signal <tempi> is never used or assigned.WARNING:Xst:1780 - Signal <tempr> is never used or assigned.    Found 16-bit register for signal <qi>.    Found 16-bit register for signal <qr>.    Found 1-bit register for signal <rdy>.    Summary:	inferred  33 D-type flip-flop(s).Unit <jiewei> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 3 1-bit register                    : 1 16-bit register                   : 2==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <jiewei> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block jiewei, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : jiewei.ngrTop Level Output File Name         : jieweiOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 99Macro Statistics :# Registers                        : 3#      1-bit register              : 1#      16-bit register             : 2Cell Usage :# BELS                             : 2#      INV                         : 1#      VCC                         : 1# FlipFlops/Latches                : 33#      FDR                         : 33# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 66#      IBUF                        : 33#      OBUF                        : 33=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5  Number of Slices:                      19  out of   3584     0%   Number of Slice Flip Flops:            33  out of   7168     0%   Number of bonded IOBs:                 99  out of    141    70%   Number of GCLKs:                        1  out of      8    12%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 33    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5   Minimum period: No path found   Minimum input arrival time before clock: 4.347ns   Maximum output required time after clock: 6.216ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'  Total number of paths / destination ports: 65 / 65-------------------------------------------------------------------------Offset:              4.347ns (Levels of Logic = 2)  Source:            start (PAD)  Destination:       rdy (FF)  Destination Clock: clk rising  Data Path: start to rdy                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             1   0.715   0.681  start_IBUF (start_IBUF)     INV:I->O             33   0.479   1.580  rdy_N01_INV_0 (rdy_N0)     FDR:R                     0.892          rdy    ----------------------------------------    Total                      4.347ns (2.086ns logic, 2.261ns route)                                       (48.0% logic, 52.0% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'  Total number of paths / destination ports: 33 / 33-------------------------------------------------------------------------Offset:              6.216ns (Levels of Logic = 1)  Source:            rdy (FF)  Destination:       rdy (PAD)  Source Clock:      clk rising  Data Path: rdy to rdy                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q              1   0.626   0.681  rdy (rdy_OBUF)     OBUF:I->O                 4.909          rdy_OBUF (rdy)    ----------------------------------------    Total                      6.216ns (5.535ns logic, 0.681ns route)                                       (89.0% logic, 11.0% route)=========================================================================CPU : 7.94 / 8.83 s | Elapsed : 7.00 / 8.00 s --> Total memory usage is 101572 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    4 (   0 filtered)Number of infos    :    0 (   0 filtered)