Release 7.1.03i - xst H.41Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 1.05 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 1.05 s | Elapsed : 0.00 / 1.00 s --> Reading design: eexy.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "eexy.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "eexy"Output Format                      : NGCTarget Device                      : xc3s400-5-pq208---- Source OptionsTop Module Name                    : eexyAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : eexy.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "../complexmul.v"Module <complexmul> compiledModule <mult> compiledCompiling verilog file "../cutbit/jiewei.v"Module <jiewei> compiledCompiling verilog file "eexy.v"Module <eexy> compiledWARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 No errors in compilationAnalysis of file <"eexy.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 Analyzing top module <eexy>.Module <eexy> is correct for synthesis. Analyzing module <complexmul>.WARNING:Xst:905 - "../complexmul.v" line 32: The signals <rdy1, rdy2, rdy3, rdy4> are missing in the sensitivity list of always block.Module <complexmul> is correct for synthesis. Analyzing module <mult>.WARNING:Xst:854 - "../complexmul.v" line 78: Ignored initial statement.Module <mult> is correct for synthesis. Analyzing module <jiewei>.Module <jiewei> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mult>.    Related source file is "../complexmul.v".WARNING:Xst:1780 - Signal <dj> is never used or assigned.    Found 1-bit register for signal <rdy>.    Found 32-bit register for signal <out>.    Found 16x16-bit multiplier for signal <$n0002> created at line 105.    Found 16-bit adder for signal <$n0004> created at line 94.    Found 16-bit adder for signal <$n0005> created at line 100.    Found 32-bit adder for signal <$n0006> created at line 109.    Found 16-bit register for signal <ain>.    Found 16-bit register for signal <bin>.    Found 32-bit register for signal <outab>.    Found 1-bit xor2 for signal <tk>.    Summary:	inferred  97 D-type flip-flop(s).	inferred   3 Adder/Subtractor(s).	inferred   1 Multiplier(s).Unit <mult> synthesized.Synthesizing Unit <jiewei>.    Related source file is "../cutbit/jiewei.v".WARNING:Xst:647 - Input <ai<9:0>> is never used.WARNING:Xst:647 - Input <ar<9:0>> is never used.    Found 16-bit register for signal <qi>.    Found 16-bit register for signal <qr>.    Found 1-bit register for signal <rdy>.    Summary:	inferred  33 D-type flip-flop(s).Unit <jiewei> synthesized.Synthesizing Unit <complexmul>.    Related source file is "../complexmul.v".    Found 32-bit subtractor for signal <$n0000> created at line 35.    Found 32-bit adder for signal <$n0001> created at line 36.    Summary:	inferred   2 Adder/Subtractor(s).Unit <complexmul> synthesized.Synthesizing Unit <eexy>.    Related source file is "eexy.v".    Found 16-bit adder for signal <$n0000> created at line 32.    Summary:	inferred   1 Adder/Subtractor(s).Unit <eexy> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...    Found registered multiplier on signal <_n0002>:	- 1 register level(s) found in a register connected to the multiplier macro ouput.	  Pushing register(s) into the multiplier macro.Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Multipliers                      : 32 16x16-bit registered multiplier   : 32# Adders/Subtractors               : 113 16-bit adder                      : 65 32-bit adder                      : 40 32-bit subtractor                 : 8# Registers                        : 152 1-bit register                    : 40 16-bit register                   : 80 32-bit register                   : 32# Xors                             : 32 1-bit xor2                        : 32==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <eexy> ...Optimizing unit <complexmul> ...Optimizing unit <jiewei> ...Optimizing unit <mult> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Register <mulw1/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw1/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw1/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw2/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw8/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw2/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw2/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw2/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw8/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw3/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw3/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw3/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw8/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw3/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw4/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw4/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw8/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw4/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw4/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw5/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw7/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw5/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw5/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw5/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw7/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw6/u4/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw6/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw6/u2/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw7/u3/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw6/u1/rdy> equivalent to <mulw1/u4/rdy> has been removedRegister <mulw7/u4/rdy> equivalent to <mulw1/u4/rdy> has been removed