?? gwwave.ant
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1.03i
// \ \ Application : ISE Foundation
// / / Filename : gwwave.ant
// /___/ /\ Timestamp : Sat Jun 02 22:38:07 2007
// \ \ / \
// \___\/\___\
//
//Command:
//Design Name: gwwave
//Device: Xilinx
//
`timescale 1ns/1ps
module gwwave;
reg [15:0] mux2 = 16'b0000000000000000;
reg [15:0] eer = 16'b0000000000000000;
reg [15:0] eei = 16'b0000000000000000;
reg [15:0] w0r = 16'b0000000000000000;
reg [15:0] w0i = 16'b0000000000000000;
reg [15:0] w1r = 16'b0000000000000000;
reg [15:0] w1i = 16'b0000000000000000;
reg [15:0] w2r = 16'b0000000000000000;
reg [15:0] w2i = 16'b0000000000000000;
reg [15:0] w3r = 16'b0000000000000000;
reg [15:0] w3i = 16'b0000000000000000;
reg [15:0] w4r = 16'b0000000000000000;
reg [15:0] w4i = 16'b0000000000000000;
reg [15:0] w5r = 16'b0000000000000000;
reg [15:0] w5i = 16'b0000000000000000;
reg [15:0] w6r = 16'b0000000000000000;
reg [15:0] w6i = 16'b0000000000000000;
reg [15:0] w7r = 16'b0000000000000000;
reg [15:0] w7i = 16'b0000000000000000;
reg [15:0] yx0r = 16'b0000000000000000;
reg [15:0] yx0i = 16'b0000000000000000;
reg [15:0] yx1r = 16'b0000000000000000;
reg [15:0] yx1i = 16'b0000000000000000;
reg [15:0] yx2r = 16'b0000000000000000;
reg [15:0] yx2i = 16'b0000000000000000;
reg [15:0] yx3r = 16'b0000000000000000;
reg [15:0] yx3i = 16'b0000000000000000;
reg [15:0] yx4r = 16'b0000000000000000;
reg [15:0] yx4i = 16'b0000000000000000;
reg [15:0] yx5r = 16'b0000000000000000;
reg [15:0] yx5i = 16'b0000000000000000;
reg [15:0] yx6r = 16'b0000000000000000;
reg [15:0] yx6i = 16'b0000000000000000;
reg [15:0] yx7r = 16'b0000000000000000;
reg [15:0] yx7i = 16'b0000000000000000;
wire [15:0] wn0r;
wire [15:0] wn0i;
wire [15:0] wn1r;
wire [15:0] wn1i;
wire [15:0] wn2r;
wire [15:0] wn2i;
wire [15:0] wn3r;
wire [15:0] wn3i;
wire [15:0] wn4r;
wire [15:0] wn4i;
wire [15:0] wn5r;
wire [15:0] wn5i;
wire [15:0] wn6r;
wire [15:0] wn6i;
wire [15:0] wn7r;
wire [15:0] wn7i;
reg clk = 1'b0;
reg start = 1'b0;
wire rdy;
parameter PERIOD = 200;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
gw UUT (
.mux2(mux2),
.eer(eer),
.eei(eei),
.w0r(w0r),
.w0i(w0i),
.w1r(w1r),
.w1i(w1i),
.w2r(w2r),
.w2i(w2i),
.w3r(w3r),
.w3i(w3i),
.w4r(w4r),
.w4i(w4i),
.w5r(w5r),
.w5i(w5i),
.w6r(w6r),
.w6i(w6i),
.w7r(w7r),
.w7i(w7i),
.yx0r(yx0r),
.yx0i(yx0i),
.yx1r(yx1r),
.yx1i(yx1i),
.yx2r(yx2r),
.yx2i(yx2i),
.yx3r(yx3r),
.yx3i(yx3i),
.yx4r(yx4r),
.yx4i(yx4i),
.yx5r(yx5r),
.yx5i(yx5i),
.yx6r(yx6r),
.yx6i(yx6i),
.yx7r(yx7r),
.yx7i(yx7i),
.wn0r(wn0r),
.wn0i(wn0i),
.wn1r(wn1r),
.wn1i(wn1i),
.wn2r(wn2r),
.wn2i(wn2i),
.wn3r(wn3r),
.wn3i(wn3i),
.wn4r(wn4r),
.wn4i(wn4i),
.wn5r(wn5r),
.wn5i(wn5i),
.wn6r(wn6r),
.wn6i(wn6i),
.wn7r(wn7r),
.wn7i(wn7i),
.clk(clk),
.start(start),
.rdy(rdy));
integer TX_FILE = 0;
integer TX_ERROR = 0;
initial begin // Annotation process for clock clk
#0;
ANNOTATE_wn0r;
ANNOTATE_wn0i;
ANNOTATE_wn1r;
ANNOTATE_wn1i;
ANNOTATE_wn2r;
ANNOTATE_wn2i;
ANNOTATE_wn3r;
ANNOTATE_wn3i;
ANNOTATE_wn4r;
ANNOTATE_wn4i;
ANNOTATE_wn5r;
ANNOTATE_wn5i;
ANNOTATE_wn6r;
ANNOTATE_wn6i;
ANNOTATE_wn7r;
ANNOTATE_wn7i;
ANNOTATE_rdy;
#OFFSET;
forever begin
#115;
ANNOTATE_wn0r;
ANNOTATE_wn0i;
ANNOTATE_wn1r;
ANNOTATE_wn1i;
ANNOTATE_wn2r;
ANNOTATE_wn2i;
ANNOTATE_wn3r;
ANNOTATE_wn3i;
ANNOTATE_wn4r;
ANNOTATE_wn4i;
ANNOTATE_wn5r;
ANNOTATE_wn5i;
ANNOTATE_wn6r;
ANNOTATE_wn6i;
ANNOTATE_wn7r;
ANNOTATE_wn7i;
ANNOTATE_rdy;
#85;
end
end
initial begin // Open the annotations file...
TX_FILE = $fopen("F:\\myfpga\\xilinx\\wopt\\gwwave.ano");
#10200 // Final time: 10200 ns
$display("Success! Annotation Simulation Complete.");
$fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
$fclose(TX_FILE);
$finish;
end
initial begin
// ------------- Current Time: 85ns
#85;
mux2 = 16'b0000000011110000;
eer = 16'b0000100010101111;
eei = 16'b0001010111110100;
w2r = 16'b0000100100110010;
w3i = 16'b0001100001100011;
yx6r = 16'b0000000111110110;
yx6i = 16'b0000000011100110;
// -------------------------------------
// ------------- Current Time: 285ns
#200;
w0r = 16'b0000000101011110;
w1r = 16'b0000001000100110;
w1i = 16'b0000001000110000;
w2i = 16'b0000001110111100;
w3r = 16'b0001001111101111;
w4r = 16'b0000110111000000;
w4i = 16'b0000100101100011;
w5r = 16'b0000110010001010;
w5i = 16'b0001000000011000;
w6r = 16'b0000000001010101;
w6i = 16'b0000000000000101;
w7r = 16'b0000000101000000;
w7i = 16'b0000000101100100;
yx0r = 16'b0001100001010110;
yx0i = 16'b0000110111000000;
yx1r = 16'b0000110111000000;
yx1i = 16'b0000000001000001;
yx2r = 16'b0000000000001010;
yx2i = 16'b0000100001010010;
yx3r = 16'b0000000000010100;
yx3i = 16'b0000110010110010;
yx4r = 16'b0000000000100000;
yx4i = 16'b0000000000001000;
yx5r = 16'b0000110111101000;
yx5i = 16'b0000000001001110;
yx7r = 16'b0000000011100110;
yx7i = 16'b0000000000100011;
// -------------------------------------
// ------------- Current Time: 485ns
#200;
start = 1'b1;
w0i = 16'b0000001010001010;
// -------------------------------------
end
task ANNOTATE_wn0r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn0r,%b]", $time, wn0r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn0i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn0i,%b]", $time, wn0i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn1r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn1r,%b]", $time, wn1r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn1i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn1i,%b]", $time, wn1i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn2r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn2r,%b]", $time, wn2r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn2i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn2i,%b]", $time, wn2i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn3r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn3r,%b]", $time, wn3r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn3i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn3i,%b]", $time, wn3i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn4r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn4r,%b]", $time, wn4r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn4i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn4i,%b]", $time, wn4i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn5r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn5r,%b]", $time, wn5r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn5i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn5i,%b]", $time, wn5i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn6r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn6r,%b]", $time, wn6r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn6i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn6i,%b]", $time, wn6i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn7r;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn7r,%b]", $time, wn7r);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_wn7i;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,wn7i,%b]", $time, wn7i);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
task ANNOTATE_rdy;
#0 begin
$fdisplay(TX_FILE, "Annotate[%d,rdy,%b]", $time, rdy);
$fflush(TX_FILE);
TX_ERROR = TX_ERROR + 1;
end
endtask
endmodule
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