////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.03i
//  \   \         Application : ISE Foundation
//  /   /         Filename : gykwave.ant
// /___/   /\     Timestamp : Sat Jun 02 10:17:35 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: gykwave
//Device: Xilinx
//
`timescale 1ns/1ps

module gykwave;
    reg [15:0] w0r = 16'b0000000000000000;
    reg [15:0] w0i = 16'b0000000000000000;
    reg [15:0] w1r = 16'b0000000000000000;
    reg [15:0] w1i = 16'b0000000000000000;
    reg [15:0] w2r = 16'b0000000000000000;
    reg [15:0] w2i = 16'b0000000000000000;
    reg [15:0] w3r = 16'b0000000000000000;
    reg [15:0] w3i = 16'b0000000000000000;
    reg [15:0] w4r = 16'b0000000000000000;
    reg [15:0] w4i = 16'b0000000000000000;
    reg [15:0] w5r = 16'b0000000000000000;
    reg [15:0] w5i = 16'b0000000000000000;
    reg [15:0] w6r = 16'b0000000000000000;
    reg [15:0] w6i = 16'b0000000000000000;
    reg [15:0] w7r = 16'b0000000000000000;
    reg [15:0] w7i = 16'b0000000000000000;
    reg [15:0] yx0r = 16'b0000000000000000;
    reg [15:0] yx0i = 16'b0000000000000000;
    reg [15:0] yx1r = 16'b0000000000000000;
    reg [15:0] yx1i = 16'b0000000000000000;
    reg [15:0] yx2r = 16'b0000000000000000;
    reg [15:0] yx2i = 16'b0000000000000000;
    reg [15:0] yx3r = 16'b0000000000000000;
    reg [15:0] yx3i = 16'b0000000000000000;
    reg [15:0] yx4r = 16'b0000000000000000;
    reg [15:0] yx4i = 16'b0000000000000000;
    reg [15:0] yx5r = 16'b0000000000000000;
    reg [15:0] yx5i = 16'b0000000000000000;
    reg [15:0] yx6r = 16'b0000000000000000;
    reg [15:0] yx6i = 16'b0000000000000000;
    reg [15:0] yx7r = 16'b0000000000000000;
    reg [15:0] yx7i = 16'b0000000000000000;
    wire [31:0] ykr;
    wire [31:0] yki;
    reg clk = 1'b0;
    reg start = 1'b0;
    wire rdy;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    gyk UUT (
        .w0r(w0r),
        .w0i(w0i),
        .w1r(w1r),
        .w1i(w1i),
        .w2r(w2r),
        .w2i(w2i),
        .w3r(w3r),
        .w3i(w3i),
        .w4r(w4r),
        .w4i(w4i),
        .w5r(w5r),
        .w5i(w5i),
        .w6r(w6r),
        .w6i(w6i),
        .w7r(w7r),
        .w7i(w7i),
        .yx0r(yx0r),
        .yx0i(yx0i),
        .yx1r(yx1r),
        .yx1i(yx1i),
        .yx2r(yx2r),
        .yx2i(yx2i),
        .yx3r(yx3r),
        .yx3i(yx3i),
        .yx4r(yx4r),
        .yx4i(yx4i),
        .yx5r(yx5r),
        .yx5i(yx5i),
        .yx6r(yx6r),
        .yx6i(yx6i),
        .yx7r(yx7r),
        .yx7i(yx7i),
        .ykr(ykr),
        .yki(yki),
        .clk(clk),
        .start(start),
        .rdy(rdy));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin    // Annotation process for clock clk
        #0;
        ANNOTATE_ykr;
        ANNOTATE_yki;
        ANNOTATE_rdy;
        #OFFSET;
        forever begin
            #115;
            ANNOTATE_ykr;
            ANNOTATE_yki;
            ANNOTATE_rdy;
            #85;
        end
    end

    initial begin  // Open the annotations file...
        TX_FILE = $fopen("F:\\myfpga\\xilinx\\wxy\\gykwave.ano");
        #10200 // Final time:  10200 ns
        $display("Success! Annotation Simulation Complete.");
        $fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
        $fclose(TX_FILE);
        $finish;
    end

    initial begin
        // -------------  Current Time:  85ns
        #85;
        w0r = 16'b0001011101110000;
        w0i = 16'b0001001110001000;
        w1r = 16'b0000011111010000;
        w1i = 16'b0000000100101100;
        w2r = 16'b0000000000000101;
        w2i = 16'b0000110110101100;
        w3r = 16'b0000000000001001;
        w3i = 16'b0000000000000110;
        w4r = 16'b0000000000001000;
        w4i = 16'b0000000000001000;
        w5r = 16'b0000000000001000;
        w6r = 16'b0000000000000101;
        w6i = 16'b0000000000000101;
        w7r = 16'b0000000000001000;
        w7i = 16'b0000000000000110;
        yx0r = 16'b0000000000000001;
        yx0i = 16'b0000000000000010;
        yx1r = 16'b0000000000000110;
        yx1i = 16'b0000000000000101;
        yx2r = 16'b0000000000001000;
        yx2i = 16'b0000000000000010;
        yx3r = 16'b0000000000000111;
        yx3i = 16'b0000000000001001;
        yx4r = 16'b0000000000001000;
        yx4i = 16'b0000000000001000;
        yx5r = 16'b0000000000111011;
        yx5i = 16'b0000000000001000;
        yx6r = 16'b0000000000111010;
        yx6i = 16'b0000000000000110;
        yx7r = 16'b0000000001010110;
        yx7i = 16'b0000000000110111;
        // -------------------------------------
        // -------------  Current Time:  285ns
        #200;
        start = 1'b1;
        w5i = 16'b0000000000000110;
        // -------------------------------------
    end

    task ANNOTATE_ykr;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,ykr,%b]", $time, ykr);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_yki;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,yki,%b]", $time, yki);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_rdy;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,rdy,%b]", $time, rdy);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

endmodule