version 3
f:\myfpga\xilinx\wxy\gyk.v
gyk
VERILOG
VERILOG
gykwave.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
rdy
clk
start
clk
w0i
clk
w0r
clk
w1i
clk
w1r
clk
w2i
clk
w2r
clk
w3i
clk
w3r
clk
w4i
clk
w4r
clk
w5i
clk
w5r
clk
w6i
clk
w6r
clk
w7i
clk
w7r
clk
yki
clk
ykr
clk
yx0i
clk
yx0r
clk
yx1i
clk
yx1r
clk
yx2i
clk
yx2r
clk
yx3i
clk
yx3r
clk
yx4i
clk
yx4r
clk
yx5i
clk
yx5r
clk
yx6i
clk
yx6r
clk
yx7i
clk
yx7r
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
rdy_DIFF
yki_DIFF
ykr_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
start
rdy
w0i
w0r
w1i
w1r
w2i
w2r
w3i
w3r
w4i
w4r
w5i
w5r
w6i
w6r
w7i
w7r
yx0i
yx0r
yx1i
yx1r
yx2i
yx2r
yx3i
yx3r
yx4i
yx4r
yx5i
yx5r
yx6i
yx6r
yx7i
yx7r
yki
ykr
SIGNAL_ORDER_END
-X-X-X-