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<H2>Application-Specific Integrated Circuits</H2>
<P><B>Michael John Sebastian Smith</B><BR>
ISBN 0-201-50022-1 * Hardcover * 1040 pages * 1997</P>
<H3>Table of Contents</H3>
<P><B>1 <A HREF="Book/CH01/CH01.htm">INTRODUCTION TO ASICs</A>
1</B></P>
<P><dt><A HREF="Book/CH01/CH01.1.htm">1.1 Types of ASICs</A> 4 <dd HREF="Book/CH01/CH01.1.htm"><A
HREF="Book/CH01/CH01.1.htm#pgfId=34514">1.1.1 Full-Custom ASICs</A> 5 <dd HREF="Book/CH01/CH01.1.htm#pgfId=34514"><A
HREF="Book/CH01/CH01.1.htm#pgfId=35619">1.1.2 Standard-Cell-Based ASICs</A>
6 <dd HREF="Book/CH01/CH01.1.htm#pgfId=35619"><A HREF="Book/CH01/CH01.1.htm#pgfId=34723">1.1.3
Gate-Array-Based ASICs</A> 11 <dd HREF="Book/CH01/CH01.1.htm#pgfId=34723"><A
HREF="Book/CH01/CH01.1.htm#pgfId=35071">1.1.4 Channeled Gate Array</A> 12
<dd HREF="Book/CH01/CH01.1.htm#pgfId=35071"><A HREF="Book/CH01/CH01.1.htm#pgfId=35097">1.1.5
Channelless Gate Array</A> 12 <dd HREF="Book/CH01/CH01.1.htm#pgfId=35097"><A
HREF="Book/CH01/CH01.1.htm#pgfId=35116">1.1.6 Structured Gate Array</A>
13 <dd HREF="Book/CH01/CH01.1.htm#pgfId=35116"><A HREF="Book/CH01/CH01.1.htm#pgfId=20631">1.1.7
Programmable Logic Devices</A> 14 <dd HREF="Book/CH01/CH01.1.htm#pgfId=20631"><A
HREF="Book/CH01/CH01.1.htm#pgfId=20654">1.1.8 Field-Programmable Gate Arrays</A>
16 <dt HREF="Book/CH01/CH01.1.htm#pgfId=20654"><A HREF="Book/CH01/CH01.2.htm">1.2
Design Flow</A> 16 <dt HREF="Book/CH01/CH01.2.htm"><A HREF="Book/CH01/CH01.3.htm">1.3
Case Study</A> 18 <dt HREF="Book/CH01/CH01.3.htm"><A HREF="Book/CH01/CH01.4.htm">1.4
Economics of ASICs</A> 20 <dd HREF="Book/CH01/CH01.4.htm"><A HREF="Book/CH01/CH01.4.htm#pgfId=1999">1.4.1
Comparison Between ASIC Technologies</A> 20 <dd HREF="Book/CH01/CH01.4.htm#pgfId=1999"><A
HREF="Book/CH01/CH01.4.htm#pgfId=2021">1.4.2 Product Cost</A> 20 <dd HREF="Book/CH01/CH01.4.htm#pgfId=2021"><A
HREF="Book/CH01/CH01.4.htm#pgfId=6839">1.4.3 ASIC Fixed Costs</A> 21 <dd HREF="Book/CH01/CH01.4.htm#pgfId=6839"><A
HREF="Book/CH01/CH01.4.htm#pgfId=55721">1.4.4 ASIC Variable Costs</A> 25
<dt HREF="Book/CH01/CH01.4.htm#pgfId=55721"><A HREF="Book/CH01/CH01.5.htm">1.5
ASIC Cell Libraries</A> 27 <dt HREF="Book/CH01/CH01.5.htm"><A HREF="Book/CH01/CH01.6.htm">1.6
Summary </A>30 <dt HREF="Book/CH01/CH01.6.htm"><A HREF="Book/CH01/CH01.7.htm">1.7
Problems</A> 31 <dt HREF="Book/CH01/CH01.7.htm"><A HREF="Book/CH01/CH01.8.htm">1.8
Bibliography</A> 36 <dt HREF="Book/CH01/CH01.8.htm"><A HREF="Book/CH01/CH01.9.htm">1.9
References</A> 38</P>
<P><dt><B>2 CMOS LOGIC 39</B></P>
<P><dt>2.1 CMOS Transistors 41 <dd>2.1.1 P-Channel Transistors 45 <dd>2.1.2
Velocity Saturation 45 <dd>2.1.3 SPICE Models 47 <dd>2.1.4 Logic Levels
47 <dt>2.2 The CMOS Process 49 <dd>2.2.1 Sheet Resistance 55 <dt>2.3 CMOS
Design Rules 58 <dt>2.4 Combinational Logic Cells 60 <dd>2.4.1 Pushing Bubbles
63 <dd>2.4.2 Drive Strength 65 <dd>2.4.3 Transmission Gates 66 <dd>2.4.4
Exclusive-OR Cell 69 <dt>2.5 Sequential Logic Cells 70 <dd>2.5.1 Latch 70
<dd>2.5.2 Flip-Flop 71 <dd>2.5.3 Clocked Inverter 73 <dt>2.6 Datapath Logic
Cells 75 <dd>2.6.1 Datapath Elements 77 <dd>2.6.2 Adders 79 <dd>2.6.3 A
Simple Example 85 <dd>2.6.4 Multipliers 87 <dd>2.6.5 Other Arithmetic Systems
94 <dd>2.6.6 Other Datapath Operators 95 <dt>2.7 I/O Cells 99 <dt>2.8 Cell
Compilers 102 <dt>2.9 Summary 102 <dt>2.10 Problems 103 <dt>2.11 Bibliography
113 <dt>2.12 References 114</P>
<P><dt><B>3 ASIC LIBRARY DESIGN 117</B></P>
<P><dt>3.1 Transistors as Resistors 117 <dt>3.2 Transistor Parasitic Capacitance
122 <dd>3.2.1 Junction Capacitance 124 <dd>3.2.2 Overlap Capacitance 124
<dd>3.2.3 Gate Capacitance 124 <dd>3.2.4 Input Slew Rate 126 <dt>3.3 Logical
Effort 129 <dd>3.3.1 Predicting Delay 134 <dd>3.3.2 Logical Area and Logical
Efficiency 134 <dd>3.3.3 Logical Paths 135 <dd>3.3.4 Multistage Cells 137
<dd>3.3.5 Optimum Delay 138 <dd>3.3.6 Optimum Number of Stages 140 <dt>3.4
Library-Cell Design 141 <dt>3.5 Library Architecture 142 <dt>3.6 Gate-Array
Design 144 <dt>3.7 Standard-Cell Design 150 <dt>3.8 Datapath-Cell Design
152 <dt>3.9 Summary 155 <dt>3.10 Problems 155 <dt>3.11 Bibliography 167
<dt>3.12 References 168</P>
<P><dt><B>4 PROGRAMMABLE ASICs 169</B></P>
RAM 174 <dt>4.3 EPROM and EEPROM Technology 174 <dt>4.4 Practical Issues
176 <dd>4.4.1 FPGAs in Use 177 <dt>4.5 Specifications 178 <dt>4.6 PREP Benchmarks
179 <dt>4.7 FPGA Economics 180 <dd>4.7.1 FPGA Pricing 180 <dd>4.7.2 Pricing
Examples 183 <dt>4.8 Summary 184 <dt>4.9 Problems 185 <dt>4.10 Bibliography
190 <dt>4.11 References 190</P>
<P><dt><B>5 PROGRAMMABLE ASIC LOGIC CELLS 191</B></P>
<P><dt>5.1 Actel ACT 191 <dd>5.1.1 ACT 1 Logic Module 191 <dd>5.1.2 Shannon's
Expansion Theorem 192 <dd>5.1.3 Multiplexer Logic as Function Generators
193 <dd>5.1.4 ACT 2 and ACT 3 Logic Modules 196 <dd>5.1.5 Timing Model and
Critical Path 197 <dd>5.1.6 Speed Grading 201 <dd>5.1.7 Worst-Case Timing
201 <dd>5.1.8 Actel Logic Module Analysis 204 <dt>5.2 Xilinx LCA 204 <dd>5.2.1
XC3000 CLB 204 <dd>5.2.2 XC4000 Logic Block 206 <dd>5.2.3 XC5200 Logic Block
207 <dd>5.2.4 Xilinx CLB Analysis 207 <dt>5.3 Altera FLEX 209 <dd>5.4 Altera
MAX 209 <dd>5.4.1 Logic Expanders 211 <dd>5.4.2 Timing Model 215 <dd>5.4.3
Power Dissipation in Complex PLDs 217 <dt>5.5 Summary 218 <dt>5.6 Problems
224 <dt>5.7 Bibliography 229 <dt>5.8 References 230</P>
<P><dt><B>6 PROGRAMMABLE ASIC I/O CELLS 231</B></P>
<P><dt>6.1 DC Output 232 <dd>6.1.1 Totem-Pole Output 234 <dd>6.1.2 Clamp
Diodes 235 <dt>6.2 AC Output 235 <dd>6.2.1 Supply Bounce 239 <dd>6.2.2 Transmission
Lines 240 <dt>6.3 DC Input 243 <dd>6.3.1 Noise Margins 244 <dd>6.3.2 Mixed-Voltage
Systems 246 <dt>6.4 AC Input 248 <dd>6.4.1 Metastability 249 <dt>6.5 Clock
Input 253 <dd>6.5.1 Registered Inputs 253 <dt>6.6 Power Input 255 <dd>6.6.1
Power Dissipation 256 <dd>6.6.2 Power-On Reset 258 <dt>6.7 Xilinx I/O Block
258 <dd>6.7.1 Boundary Scan 260 <dt>6.8 Other I/O Cells 261 <dt>6.9 Summary
262 <dt>6.10 Problems 263 <dt>6.11 Bibliography 272 <dt>6.12 References
273</P>
<P><dt><B>7 PROGRAMMABLE ASIC INTERCONNECT 275</B></P>
Constant 278 <dd>7.1.3 RC Delay in Antifuse Connections 280 <dd>7.1.4 Antifuse
Parasitic Capacitance 281 <dd>7.1.5 ACT 2 and ACT 3 Interconnect 283 <dt>7.2
Xilinx LCA 284 <dt>7.3 Xilinx EPLD 288 <dt>7.4 Altera MAX 5000 and 7000
289 <dt>7.5 Altera MAX 9000 290 <dt>7.6 Altera FLEX 291 <dt>7.7 Summary
292 <dt>7.8 Problems 294 <dt>7.9 Bibliography 297 <dt>7.10 References 297</P>
<P><dt><B>8 PROGRAMMABLE ASIC DESIGN SOFTWARE 299</B></P>
<P><dt>8.1 Design Systems 299 <dd>8.1.1 Xilinx 301 <dd>8.1.2 Actel 303 <dd>8.1.3
Altera 303 <dt>8.2 Logic Synthesis 304 <dd>8.2.1 FPGA Synthesis 305 <dt>8.3
The Halfgate ASIC 307 <dd>8.3.1 Xilinx 307 <dd>8.3.2 Actel 310 <dd>8.3.3
Altera 310 <dd>8.3.4 Comparison 315 <dt>8.4 Summary 316 <dt>8.5 Problems
316 <dt>8.6 Bibliography 320 <dd>8.6.1 FPGA Vendors 321 <dd>8.6.2 Third-Party
Software 323 <dt>8.7 References 326</P>
<P><dt><B>9 LOW-LEVEL DESIGN ENTRY 327</B></P>
<P><dt>9.1 Schematic Entry 328 <dd>9.1.1 Hierarchical Design 330 <dd>9.1.2
The Cell Library 330 <dd>9.1.3 Names 332 <dd>9.1.4 Schematic Icons and Symbols
333 <dd>9.1.5 Nets 336 <dd>9.1.6 Schematic Entry for ASICs and PCBs 336
<dd>9.1.7 Connections 338 <dd>9.1.8 Vectored Instances and Buses 338 <dd>9.1.9
Edit-in-Place 340 <dd>9.1.10 Attributes 341 <dd>9.1.11 Netlist Screener
341 <dd>9.1.12 Schematic-Entry tools 343 <dd>9.1.13 Back-Annotation 345
<dt>9.2 Low-Level Design Languages 345 <dd>9.2.1 ABEL 346 <dd>9.2.2 CUPL
348 <dd>9.2.3 PALASM 350 <dt>9.3 PLA Tools 353 <dt>9.4 EDIF 355 <dd>9.4.1
EDIF Syntax 355 <dd>9.4.2 An EDIF Netlist Example 357 <dd>9.4.3 An EDIF
Schematic Icon 359 <dd>9.4.4 An EDIF Example 365 <dt>9.5 CFI Design Representation
369 <dd>9.5.1 CFI Connectivity Model 370 <dt>9.6 Summary 373 <dt>9.7 Problems
373 <dt>9.8 Bibliography 376 <dt>9.9 References 377</P>
<P><dt><B>10 VHDL 379</B></P>
<P><dt>10.1 A Counter 380 <dt>10.2 A 4-bit Multiplier 381 <dd>10.2.1 An
8-bit Adder 381 <dd>10.2.2 A Register Accumulator 381 <dd>10.2.3 Zero Detector
383 <dd>10.2.4 A Shift Register 384 <dd>10.2.5 A State Machine 384 <dd>10.2.6
A Multiplier 385 <dd>10.2.7 Packages and Testbench 388 <dt>10.3 Syntax and
Semantics of VHDL 390 <dt>10.4 Identifiers and Literals 392 <dt>10.5 Entities
and Architectures 393 <dt>10.6 Packages and Libraries 398 <dd>10.6.1 Standard
Package 399 <dd>10.6.2 Std_logic_1164 Package 400 <dd>10.6.3 Textio Package
402 <dd>10.6.4 Other Packages 403 <dd>10.6.5 Creating Packages 404 <dt>10.7
Interface Declarations 405 <dd>10.7.1 Port Declaration 406 <dd>10.7.2 Generics
410 <dt>10.8 Type Declarations 411 <dt>10.9 Other Declarations 413 <dd>10.9.1
Object Declarations 414 <dd>10.9.2 Subprogram Declarations 415 <dd>10.9.3
Alias and Attribute Declarations 418 <dd>10.9.4 Predefined Attributes 419
<dt>10.10 Sequential Statements 419 <dd>10.10.1 Wait Statement 421 <dd>10.10.2
Assertion and Report Statements 423 <dd>10.10.3 Assignment Statements 424
<dd>10.10.4 Procedure Call 426 <dd>10.10.5 If Statement 427 <dd>10.10.6
Case Statement 428 <dd>10.10.7 Other Sequential Control Statements 429 <dt>10.11
Operators 430 <dt>10.12 Arithmetic 432 <dd>10.12.1 IEEE Synthesis Packages
434 <dt>10.13 Concurrent Statements 437 <dd>10.13.1 Block Statement 438
<dd>10.13.2 Process Statement 440 <dd>10.13.3 Concurrent Procedure Call
441 <dd>10.13.4 Concurrent Signal Assignment 442 <dd>10.13.5 Concurrent
Assertion Statement 443 <dd>10.13.6 Component Instantiation 444 <dd>10.13.7
Generate Statement 444 <dt>10.14 Execution 445 <dt>10.15 Configurations
and Specifications 447 <dt>10.16 An Engine Controller 449 <dt>10.17 Summary
456 <dt>10.18 Problems 459 <dt>10.19 Bibliography 477 <dt>10.20 References
478</P>
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