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<H1 CLASS="ChapterTitle">
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ROUTING</H1>
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Once the designer has floorplanned a chip and the logic cells within the flexible blocks have been placed, it is time to make the connections by routing the chip. This is still a hard problem that is made easier by dividing it into smaller problems. Routing is usually split into <A NAME="marker=454">
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<SPAN CLASS="Definition">
global routing </SPAN>
followed by <A NAME="marker=457">
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detailed routing</SPAN>
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Suppose the ASIC is North America and some travelers in California need advice on how to drive from Stanford (near San Francisco) to Caltech (near Los Angeles). The floorplanner has decided that California is on the left (west) side of the ASIC and the placement tool has put Stanford in Northern California and Caltech in Southern California. Floorplanning and placement have defined the roads and freeways. There are two ways to go: the coastal route (using Highway 101) or the inland route (using Interstate I5, which is usually faster). The global router specifies the coastal route because the travelers are not in a hurry and I5 is congested (the global router knows this because it has already routed onto I5 many other travelers that are in a hurry today). Next, the detailed router looks at a map and gives indications from Stanford onto Highway 101 south through San Jose, Monterey, and Santa Barbara to Los Angeles and then off the freeway to Caltech in Pasadena. </P>
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<A HREF="CH17.htm#30446" CLASS="XRef">
Figure 17.1</A>
shows the core of the Viterbi decoder after the placement step. This implementation consists entirely of standard cells (18 rows). The I/O pads are not included in this example—we can route the I/O pads after we route the core (though this is not always a good idea). <A HREF="CH17.htm#27167" CLASS="XRef">
Figure 17.2</A>
shows the Viterbi decoder chip after global and detailed routing. The routing runs in the channels between the rows of logic cells, but the individual interconnections are too small to see.</P>
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FIGURE 17.1 <A NAME="30446">
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The core of the Viterbi decoder chip after placement (a screen shot from Cadence Cell Ensemble). This is the same placement as shown in Figure 16.2, but without the channel labels. You can see the rows of standard cells; the widest cells are the D flip-flops.</P>
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FIGURE 17.2 <A NAME="27167">
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The core of the Viterbi decoder chip after the completion of global and detailed routing (a screen shot from Cadence Cell Ensemble). This chip uses two-level metal. Although you cannot see the difference, m1 runs in the horizontal direction and m2 in the vertical direction.</P>
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<H1 CLASS="Heading1TOC">
<A HREF="CH17.1.htm#pgfId=462" CLASS="Hypertext">
17.1 Global Routing</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH17.2.htm#pgfId=718" CLASS="Hypertext">
17.2 Detailed Routing</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH17.3.htm#pgfId=14363" CLASS="Hypertext">
17.3 Special Routing</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH17.4.htm#pgfId=17235" CLASS="Hypertext">
17.4 Circuit Extraction and DRC</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH17.5.htm#pgfId=1321" CLASS="Hypertext">
17.5 Summary</A>
</H1>
<H1 CLASS="Heading1TOC">
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17.6 Problems</A>
</H1>
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17.7 <SPAN CLASS="Emphasis">
</SPAN>
Bibliography</A>
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<A HREF="CH17.8.htm#pgfId=50992" CLASS="Hypertext">
17.8 References</A>
</H1>
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