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<H1 CLASS="Heading1">
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9.1 <A NAME="10432">
</A>
Schematic Entry</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=2438">
</A>
<SPAN CLASS="Definition">
Schematic entry</SPAN>
<A NAME="marker=2436">
</A>
is the most common method of design entry for ASICs and is likely to be useful in one form or another for some time. HDLs are replacing conventional gate-level schematic entry, but new graphical tools based on schematic entry are now being used to create large amounts of HDL code.</P>
<P CLASS="Body">
<A NAME="pgfId=32019">
</A>
Circuit schematics are drawn on <A NAME="marker=2456">
</A>
<SPAN CLASS="Definition">
schematic sheets</SPAN>
. Standard schematic sheet sizes (<A HREF="#28809" CLASS="XRef">
Table 9.1</A>
) are <A NAME="marker=20757">
</A>
ANSI A–E (more common in the United States) and <A NAME="marker=20756">
</A>
ISO A4–A0 (more common in Europe). Usually a <A NAME="marker=2459">
</A>
<SPAN CLASS="Definition">
frame</SPAN>
or <A NAME="marker=2461">
</A>
<SPAN CLASS="Definition">
border</SPAN>
is drawn around the schematic containing boxes that list the name and number of the schematic page, the designer, the date of the drawing, and a list of any modifications or changes.</P>
<TABLE>
<TR>
<TH ROWSPAN="1" COLSPAN="4">
<P CLASS="TableTitle">
<A NAME="pgfId=6040">
</A>
TABLE 9.1 <A NAME="28809">
</A>
ANSI (American National Standards Institute) and ISO (International Standards Organization) schematic sheet sizes.</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6048">
</A>
<SPAN CLASS="TableHeads">
ANSI sheet</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6050">
</A>
<SPAN CLASS="TableHeads">
Size (inches)</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6052">
</A>
<SPAN CLASS="TableHeads">
ISO sheet</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=6054">
</A>
<SPAN CLASS="TableHeads">
Size (cm)</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6056">
</A>
A</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6058">
</A>
8.5 <SPAN CLASS="Symbol">
¥ </SPAN>
11</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6060">
</A>
A5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6062">
</A>
21.0 <SPAN CLASS="Symbol">
¥</SPAN>
14.8</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6064">
</A>
B</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6066">
</A>
11 <SPAN CLASS="Symbol">
¥</SPAN>
17</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8295">
</A>
A4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6070">
</A>
29.7 <SPAN CLASS="Symbol">
¥</SPAN>
21.0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6072">
</A>
C</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6074">
</A>
17 <SPAN CLASS="Symbol">
¥</SPAN>
22</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8297">
</A>
A3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6078">
</A>
42.0 <SPAN CLASS="Symbol">
¥</SPAN>
29.7</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6080">
</A>
D</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6082">
</A>
22 <SPAN CLASS="Symbol">
¥</SPAN>
34</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8299">
</A>
A2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6086">
</A>
59.4 <SPAN CLASS="Symbol">
¥</SPAN>
42.0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6088">
</A>
E</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6090">
</A>
34 <SPAN CLASS="Symbol">
¥</SPAN>
44</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8301">
</A>
A1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=6094">
</A>
84.0 <SPAN CLASS="Symbol">
¥</SPAN>
59.4</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8287">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8289">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8303">
</A>
A0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=8293">
</A>
118.9 <SPAN CLASS="Symbol">
¥</SPAN>
84.0</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=6125">
</A>
<A HREF="#24739" CLASS="XRef">
Figure 9.1</A>
shows the “<A NAME="marker=20743">
</A>
spades” and “<A NAME="marker=20746">
</A>
shovels,” the recognized symbols for AND, NAND, OR, and NOR gates. One of the problems with these recommendations is that the corner points of the shapes do not always lie on a grid point (using a reasonable grid size). </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=6136">
</A>
<IMG SRC="CH09-1.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=6138">
</A>
FIGURE 9.1 <A NAME="24739">
</A>
IEEE-recommended dimensions and their construction for logic-gate symbols. (a) NAND gate (b) exclusive-OR gate (an OR gate is a subset).</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=29273">
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