library verilog;use verilog.vl_types.all;entity txd is    generic(        TX_IDLE         : integer := 1;        TX_READY        : integer := 2;        TX_START        : integer := 4;        TX_DATA         : integer := 8;        TX_PARITY       : integer := 16;        TX_STOP1        : integer := 32;        TX_STOP2        : integer := 64;        TX_DONE         : integer := 128    );    port(        clk             : in     vl_logic;        rst_n           : in     vl_logic;        clk_en          : in     vl_logic;        data_i          : in     vl_logic_vector(7 downto 0);        enable          : in     vl_logic;        txd_xo          : out    vl_logic;        ctrl_i          : in     vl_logic_vector(4 downto 0);        frame_bits_i    : in     vl_logic_vector(3 downto 0);        stat_o          : out    vl_logic_vector(1 downto 0);        busy_o          : out    vl_logic    );end txd;