?? uart.pin
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V or 3.0V depending on the needs of the configuration device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10 kohm resistor
-- to GND or tie all pins together and connect through a single 10 kohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
CHIP "uart" ASSIGNED TO AN: EP1C3T144C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND* : 1 : : : : 1 :
GND* : 2 : : : : 1 :
GND* : 3 : : : : 1 :
GND* : 4 : : : : 1 :
GND* : 5 : : : : 1 :
GND* : 6 : : : : 1 :
GND* : 7 : : : : 1 :
VCCIO1 : 8 : power : : 3.3V : 1 :
GND : 9 : gnd : : : :
GND* : 10 : : : : 1 :
GND* : 11 : : : : 1 :
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 12 : input : 3.3-V LVTTL : : 1 : N
DATA0 : 13 : input : : : 1 :
nCONFIG : 14 : : : : 1 :
VCCA_PLL1 : 15 : power : : 1.5V : :
clk : 16 : input : 3.3-V LVTTL : : 1 : Y
GND+ : 17 : : : : 1 :
GNDA_PLL1 : 18 : gnd : : : :
GNDG_PLL1 : 19 : gnd : : : :
nCEO : 20 : : : : 1 :
nCE : 21 : : : : 1 :
MSEL0 : 22 : : : : 1 :
MSEL1 : 23 : : : : 1 :
DCLK : 24 : bidir : : : 1 :
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 25 : input : 3.3-V LVTTL : : 1 : N
GND* : 26 : : : : 1 :
GND* : 27 : : : : 1 :
GND* : 28 : : : : 1 :
VCCIO1 : 29 : power : : 3.3V : 1 :
GND : 30 : gnd : : : :
GND* : 31 : : : : 1 :
rxd : 32 : input : 3.3-V LVTTL : : 1 : Y
txd : 33 : output : 3.3-V LVTTL : : 1 : Y
GND* : 34 : : : : 1 :
GND* : 35 : : : : 1 :
GND* : 36 : : : : 1 :
int_o : 37 : output : 3.3-V LVTTL : : 4 : Y
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