?? fpga_pro.tan.rpt
字號:
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 290.19 MHz ( period = 3.446 ns ) ; gollman:inst|iena ; gollman:inst|src[1] ; clk ; clk ; None ; None ; 3.165 ns ;
; N/A ; 290.19 MHz ( period = 3.446 ns ) ; gollman:inst|iena ; gollman:inst|src[0] ; clk ; clk ; None ; None ; 3.165 ns ;
; N/A ; 307.31 MHz ( period = 3.254 ns ) ; gollman:inst|enac ; gollman:inst|src[1] ; clk ; clk ; None ; None ; 2.973 ns ;
; N/A ; 307.31 MHz ( period = 3.254 ns ) ; gollman:inst|enac ; gollman:inst|src[0] ; clk ; clk ; None ; None ; 2.973 ns ;
; N/A ; 325.41 MHz ( period = 3.073 ns ) ; gollman:inst|iena ; gollman:inst|srb[1] ; clk ; clk ; None ; None ; 2.812 ns ;
; N/A ; 325.41 MHz ( period = 3.073 ns ) ; gollman:inst|iena ; gollman:inst|srb[2] ; clk ; clk ; None ; None ; 2.812 ns ;
; N/A ; 325.41 MHz ( period = 3.073 ns ) ; gollman:inst|iena ; gollman:inst|srb[0] ; clk ; clk ; None ; None ; 2.812 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[0] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[1] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[2] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[3] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[4] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[5] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[6] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[7] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[8] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[9] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[10] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|iena ; gollman:inst|srd[11] ; clk ; clk ; None ; None ; 2.622 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[0] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[1] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[2] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[3] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[4] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[5] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[6] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[7] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[8] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[9] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[10] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enad ; gollman:inst|srd[11] ; clk ; clk ; None ; None ; 2.582 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; lpm_counter0:inst6|lpm_counter:lpm_counter_component|cntr_ihi:auto_generated|safe_q[0] ; lpm_counter0:inst6|lpm_counter:lpm_counter_component|cntr_ihi:auto_generated|safe_q[7] ; clk ; clk ; None ; None ; 2.319 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enab ; gollman:inst|srb[1] ; clk ; clk ; None ; None ; 2.242 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; gollman:inst|enab ; gollman:inst|srb[2] ; clk ; clk ; None ; None ; 2.242 ns ;
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