module gollman( clk,reset,ena,data,done);//,iena),enab,enac,enad );

parameter	keya = 7'b1011011;	//1st LFR key
parameter	keyb = 4'b1001;	//2nd LFR key
parameter	keyc = 3'b011;	//3rd LFR key
parameter	keyd = 12'b011010111010;	//4th LFR key

/*
//test output
output iena;
output enab;
output enac;
output enad;
*/


output data;
output done;

input reset;
input ena;
input clk;

reg	[6:0] sra;	//1st LFR instantiation
reg [3:0] srb;	//2nd
reg [2:0] src;	//3nd
reg [11:0] srd;	//4nd

reg	enab;	//Clock enables for cascade LFRs
reg	enac;
reg	enad;

reg	last_ena;	//Registered 'ena
reg	donei;	//internal 'done' node

reg	iena;	//internal 'single clock' ena
reg	oena;	//registered version of ena - for edge detect

reg done;
reg data;
 
//Process to edge detect enable signal to generate single clock duration enable
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			begin
				iena <= 1'b0;
				oena <= 1'b0;
			end
		else
			begin
				oena <= ena;
				if( ena == 1'b1 & oena == 1'b0 )
					iena <= 1'b1;
				else
					iena <= 1'b0;
			end
	end
	
//Implementation of 1st LFR in this cascade
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			sra <= keya;
		else
			begin
			if( iena == 1'b1 )
				begin
				sra[5:0] <= sra[6:1];	//Perform Shift
				sra[6] <= sra[6] ^ sra[2];
//				xor a1(sra[6],sra[6],sra[2]);	//XOR bits 6,2 for maximal
				end
			else
				begin
				sra <= sra;
				end
			enab <= ~sra[1];
			end
	end

//Implementation of 2nd LFR in this cascade
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			srb <= keyb;
		else
			begin
			if( iena == 1'b1 & enab == 1'b1 )
				begin
				srb[2:0] <= srb[3:1];
				srb[3] <= srb[3] ^ srb[0];
//				xor a2(srb[3], srb[3],srb[0]);
				end
			else
				begin
				srb <= srb;
				end
			enac <= (~sra[1]) ^ srb[1];
//			xor a3(enac,(~sra[1]),srb[1]);
			end
	end

//Implementation of 3rd LFR in cascade
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			src <= keyc;
		else
			begin
			if( iena == 1'b1 & enac == 1'b1 )
				begin
				src[1:0] <= src[2:1];
				src[2] <= src[2] ^ src[0];
//				xor a4(src[2],src[2],src[0]);
				end
			else
				begin
				src <= src;
				end
			enad <= (~sra[1]) ^ srb[1] ^ src[1];
//			xor a5(enad,(~sra[1]),srb[1],src[1]);
			end
	end

//Implementation of 4th LFR in cascade
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			srd <= keyd;
		else
			begin
				if( iena == 1'b1 & enad == 1'b1 )
					begin
					srd[10:0] <= srd[11:1];
					srd[11] <= srd[11] ^ srd[5] ^ srd[3] ^ srd[0];
//					xor a6(srd[11],srd[11],srd[5],srd[3],srd[0]);
//XOR bits 11,5,3,0 for maximal length
					end
				else
					begin
					srd <= srd;
					end
			end
		data <= srd[0];
	end
/*	
-- Simple process to handle DONE signal in this h/w implementation
-- In order to be compatible with a microprocessor-type implementation, this process
-- implements a handshake. Done goes Low after ENA goes high, and then High after
-- ENA goes low. As this is hardware, the result is available immediately, but in a
-- micro, done would go high once the next result is available, ie. many clocks after ENA
-- goes low.
-- The top-level schematic handles the other side of the handshake.
*/
always@( posedge clk or negedge reset )
	begin
		if( !reset )
			donei <= 1'b1;
		else
			begin
			last_ena <= ena;
			if( ena == 1'b1 & last_ena == 1'b0 )
				donei <= 1'b0;
			else
				if( iena == 1'b0 & last_ena == 1'b1 )
					donei <= 1'b1;
				else
					donei <= donei;
			end
		done <= donei;
	end

endmodule