; N/A   ; None         ; 7.824 ns   ; enad~reg0 ; enad ; clk        ;
; N/A   ; None         ; 7.804 ns   ; srd[0]    ; data ; clk        ;
; N/A   ; None         ; 7.754 ns   ; enac~reg0 ; enac ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; -0.369 ns ; reset ; enad~reg0 ; clk      ;
; N/A           ; None        ; -0.369 ns ; reset ; enac~reg0 ; clk      ;
; N/A           ; None        ; -0.457 ns ; reset ; enab~reg0 ; clk      ;
; N/A           ; None        ; -0.457 ns ; reset ; last_ena  ; clk      ;
; N/A           ; None        ; -4.579 ns ; ena   ; oena      ; clk      ;
; N/A           ; None        ; -4.599 ns ; ena   ; iena~reg0 ; clk      ;
; N/A           ; None        ; -4.818 ns ; ena   ; last_ena  ; clk      ;
; N/A           ; None        ; -5.280 ns ; ena   ; donei     ; clk      ;
+---------------+-------------+-----------+-------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Aug 15 09:45:43 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off gollman -c gollman --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "iena~reg0" and destination register "srb[1]"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.550 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'
            Info: 2: + IC(1.170 ns) + CELL(0.206 ns) = 1.376 ns; Loc. = LCCOMB_X21_Y7_N10; Fanout = 3; COMB Node = 'always2~0'
            Info: 3: + IC(0.319 ns) + CELL(0.855 ns) = 2.550 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 3; REG Node = 'srb[1]'
            Info: Total cell delay = 1.061 ns ( 41.61 % )
            Info: Total interconnect delay = 1.489 ns ( 58.39 % )
        Info: - Smallest clock skew is -0.014 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.774 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.825 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 3; REG Node = 'srb[1]'
                Info: Total cell delay = 1.806 ns ( 65.10 % )
                Info: Total interconnect delay = 0.968 ns ( 34.90 % )
            Info: - Longest clock path from clock "clk" to source register is 2.788 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'
                Info: Total cell delay = 1.806 ns ( 64.78 % )
                Info: Total interconnect delay = 0.982 ns ( 35.22 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "donei" (data pin = "ena", clock pin = "clk") is 5.546 ns
    Info: + Longest pin to register delay is 8.374 ns
        Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_169; Fanout = 4; PIN Node = 'ena'
        Info: 2: + IC(6.631 ns) + CELL(0.651 ns) = 8.266 ns; Loc. = LCCOMB_X21_Y8_N20; Fanout = 1; COMB Node = 'donei~63'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.374 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 2; REG Node = 'donei'
        Info: Total cell delay = 1.743 ns ( 20.81 % )
        Info: Total interconnect delay = 6.631 ns ( 79.19 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.788 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 2; REG Node = 'donei'
        Info: Total cell delay = 1.806 ns ( 64.78 % )
        Info: Total interconnect delay = 0.982 ns ( 35.22 % )
Info: tco from clock "clk" to destination pin "iena" through register "iena~reg0" is 8.847 ns
    Info: + Longest clock path from clock "clk" to source register is 2.788 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'
        Info: Total cell delay = 1.806 ns ( 64.78 % )
        Info: Total interconnect delay = 0.982 ns ( 35.22 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.755 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'
        Info: 2: + IC(2.499 ns) + CELL(3.256 ns) = 5.755 ns; Loc. = PIN_185; Fanout = 0; PIN Node = 'iena'
        Info: Total cell delay = 3.256 ns ( 56.58 % )
        Info: Total interconnect delay = 2.499 ns ( 43.42 % )
Info: th for register "enad~reg0" (data pin = "reset", clock pin = "clk") is -0.369 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y8_N15; Fanout = 2; REG Node = 'enad~reg0'
        Info: Total cell delay = 1.806 ns ( 64.80 % )
        Info: Total interconnect delay = 0.981 ns ( 35.20 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.462 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.477 ns) + CELL(0.855 ns) = 3.462 ns; Loc. = LCFF_X20_Y8_N15; Fanout = 2; REG Node = 'enad~reg0'
        Info: Total cell delay = 1.985 ns ( 57.34 % )
        Info: Total interconnect delay = 1.477 ns ( 42.66 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 118 megabytes of memory during processing
    Info: Processing ended: Fri Aug 15 09:45:45 2008
    Info: Elapsed time: 00:00:02