?? gollman.tan.qmsg
字號(hào):
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register iena~reg0 srb\[1\] 340.02 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 340.02 MHz between source register \"iena~reg0\" and destination register \"srb\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.550 ns + Longest register register " "Info: + Longest register to register delay is 2.550 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iena~reg0 1 REG LCFF_X21_Y8_N23 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iena~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.170 ns) + CELL(0.206 ns) 1.376 ns always2~0 2 COMB LCCOMB_X21_Y7_N10 3 " "Info: 2: + IC(1.170 ns) + CELL(0.206 ns) = 1.376 ns; Loc. = LCCOMB_X21_Y7_N10; Fanout = 3; COMB Node = 'always2~0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.376 ns" { iena~reg0 always2~0 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.855 ns) 2.550 ns srb\[1\] 3 REG LCFF_X21_Y7_N13 3 " "Info: 3: + IC(0.319 ns) + CELL(0.855 ns) = 2.550 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 3; REG Node = 'srb\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.174 ns" { always2~0 srb[1] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 41.61 % ) " "Info: Total cell delay = 1.061 ns ( 41.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.489 ns ( 58.39 % ) " "Info: Total interconnect delay = 1.489 ns ( 58.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.550 ns" { iena~reg0 always2~0 srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.550 ns" { iena~reg0 {} always2~0 {} srb[1] {} } { 0.000ns 1.170ns 0.319ns } { 0.000ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.774 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.666 ns) 2.774 ns srb\[1\] 3 REG LCFF_X21_Y7_N13 3 " "Info: 3: + IC(0.825 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X21_Y7_N13; Fanout = 3; REG Node = 'srb\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { clk~clkctrl srb[1] } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.10 % ) " "Info: Total cell delay = 1.806 ns ( 65.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 34.90 % ) " "Info: Total interconnect delay = 0.968 ns ( 34.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk {} clk~combout {} clk~clkctrl {} srb[1] {} } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.788 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns iena~reg0 3 REG LCFF_X21_Y8_N23 13 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl iena~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl iena~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} iena~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk {} clk~combout {} clk~clkctrl {} srb[1] {} } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl iena~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} iena~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.550 ns" { iena~reg0 always2~0 srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.550 ns" { iena~reg0 {} always2~0 {} srb[1] {} } { 0.000ns 1.170ns 0.319ns } { 0.000ns 0.206ns 0.855ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { clk clk~clkctrl srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { clk {} clk~combout {} clk~clkctrl {} srb[1] {} } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl iena~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} iena~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { srb[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { srb[1] {} } { } { } "" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 99 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TSU_RESULT" "donei ena clk 5.546 ns register " "Info: tsu for register \"donei\" (data pin = \"ena\", clock pin = \"clk\") is 5.546 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.374 ns + Longest pin register " "Info: + Longest pin to register delay is 8.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns ena 1 PIN PIN_169 4 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_169; Fanout = 4; PIN Node = 'ena'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.631 ns) + CELL(0.651 ns) 8.266 ns donei~63 2 COMB LCCOMB_X21_Y8_N20 1 " "Info: 2: + IC(6.631 ns) + CELL(0.651 ns) = 8.266 ns; Loc. = LCCOMB_X21_Y8_N20; Fanout = 1; COMB Node = 'donei~63'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.282 ns" { ena donei~63 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 168 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.374 ns donei 3 REG LCFF_X21_Y8_N21 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.374 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 2; REG Node = 'donei'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { donei~63 donei } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 168 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.743 ns ( 20.81 % ) " "Info: Total cell delay = 1.743 ns ( 20.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.631 ns ( 79.19 % ) " "Info: Total interconnect delay = 6.631 ns ( 79.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.374 ns" { ena donei~63 donei } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.374 ns" { ena {} ena~combout {} donei~63 {} donei {} } { 0.000ns 0.000ns 6.631ns 0.000ns } { 0.000ns 0.984ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 168 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.788 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns donei 3 REG LCFF_X21_Y8_N21 2 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 2; REG Node = 'donei'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl donei } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 168 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl donei } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} donei {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.374 ns" { ena donei~63 donei } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.374 ns" { ena {} ena~combout {} donei~63 {} donei {} } { 0.000ns 0.000ns 6.631ns 0.000ns } { 0.000ns 0.984ns 0.651ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl donei } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} donei {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk iena iena~reg0 8.847 ns register " "Info: tco from clock \"clk\" to destination pin \"iena\" through register \"iena~reg0\" is 8.847 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.788 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns iena~reg0 3 REG LCFF_X21_Y8_N23 13 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl iena~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl iena~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} iena~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.755 ns + Longest register pin " "Info: + Longest register to pin delay is 5.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns iena~reg0 1 REG LCFF_X21_Y8_N23 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 13; REG Node = 'iena~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iena~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 56 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.499 ns) + CELL(3.256 ns) 5.755 ns iena 2 PIN PIN_185 0 " "Info: 2: + IC(2.499 ns) + CELL(3.256 ns) = 5.755 ns; Loc. = PIN_185; Fanout = 0; PIN Node = 'iena'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.755 ns" { iena~reg0 iena } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.256 ns ( 56.58 % ) " "Info: Total cell delay = 3.256 ns ( 56.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.499 ns ( 43.42 % ) " "Info: Total interconnect delay = 2.499 ns ( 43.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.755 ns" { iena~reg0 iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.755 ns" { iena~reg0 {} iena {} } { 0.000ns 2.499ns } { 0.000ns 3.256ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl iena~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} iena~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.755 ns" { iena~reg0 iena } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.755 ns" { iena~reg0 {} iena {} } { 0.000ns 2.499ns } { 0.000ns 3.256ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "Classic Timing Analyzer" 0}
{ "Info" "ITDB_TH_RESULT" "enad~reg0 reset clk -0.369 ns register " "Info: th for register \"enad~reg0\" (data pin = \"reset\", clock pin = \"clk\") is -0.369 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.787 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.787 ns enad~reg0 3 REG LCFF_X20_Y8_N15 2 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y8_N15; Fanout = 2; REG Node = 'enad~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { clk~clkctrl enad~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 121 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.80 % ) " "Info: Total cell delay = 1.806 ns ( 64.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl enad~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} enad~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 121 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.462 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 PIN PIN_24 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 5; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.855 ns) 3.462 ns enad~reg0 2 REG LCFF_X20_Y8_N15 2 " "Info: 2: + IC(1.477 ns) + CELL(0.855 ns) = 3.462 ns; Loc. = LCFF_X20_Y8_N15; Fanout = 2; REG Node = 'enad~reg0'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { reset enad~reg0 } "NODE_NAME" } } { "gollman.v" "" { Text "E:/FPGA/FPGA加密/gollman/gollman.v" 121 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.985 ns ( 57.34 % ) " "Info: Total cell delay = 1.985 ns ( 57.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.477 ns ( 42.66 % ) " "Info: Total interconnect delay = 1.477 ns ( 42.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.462 ns" { reset enad~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.462 ns" { reset {} reset~combout {} enad~reg0 {} } { 0.000ns 0.000ns 1.477ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Classic Timing Analyzer" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { clk clk~clkctrl enad~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { clk {} clk~combout {} clk~clkctrl {} enad~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.462 ns" { reset enad~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.462 ns" { reset {} reset~combout {} enad~reg0 {} } { 0.000ns 0.000ns 1.477ns } { 0.000ns 1.130ns 0.855ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Classic Timing Analyzer" 0}
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