{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 14 22:22:43 2008 " "Info: Processing started: Thu Aug 14 22:22:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gollstt -c gollstt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gollstt -c gollstt" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gollstt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file gollstt.v" { { "Info" "ISGN_ENTITY_NAME" "1 gollstt " "Info: Found entity 1: gollstt" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "gollstt " "Info: Elaborating entity \"gollstt\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|gollstt\|pres_s 4 " "Info: State machine \"\|gollstt\|pres_s\" contains 4 states" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|gollstt\|pres_s " "Info: Selected Auto state machine encoding method for state machine \"\|gollstt\|pres_s\"" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|gollstt\|pres_s " "Info: Encoding result for state machine \"\|gollstt\|pres_s\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "2 " "Info: Completed encoding using 2 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pres_s.state_bit_1 " "Info: Encoded state bit \"pres_s.state_bit_1\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "Analysis & Synthesis" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "pres_s.state_bit_0 " "Info: Encoded state bit \"pres_s.state_bit_0\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "Analysis & Synthesis" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gollstt\|pres_s.st0 00 " "Info: State \"\|gollstt\|pres_s.st0\" uses code string \"00\"" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "Analysis & Synthesis" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gollstt\|pres_s.st1 01 " "Info: State \"\|gollstt\|pres_s.st1\" uses code string \"01\"" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "Analysis & Synthesis" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gollstt\|pres_s.st2 10 " "Info: State \"\|gollstt\|pres_s.st2\" uses code string \"10\"" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "Analysis & Synthesis" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gollstt\|pres_s.st3 11 " "Info: State \"\|gollstt\|pres_s.st3\" uses code string \"11\"" {  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "Analysis & Synthesis" 0}  } { { "gollstt.v" "" { Text "E:/FPGA/FPGA加密/gollstt/gollstt.v" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Analysis & Synthesis" 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "reset " "Info: Promoted clear signal driven by pin \"reset\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "Analysis & Synthesis" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 4 " "Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "pres_s~14 " "Info: Register \"pres_s~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "pres_s~15 " "Info: Register \"pres_s~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "pres_s~16 " "Info: Register \"pres_s~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "pres_s~17 " "Info: Register \"pres_s~17\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "Analysis & Synthesis" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "Analysis & Synthesis" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "Analysis & Synthesis" 0} { "Info" "ICUT_CUT_TM_MCELLS" "4 " "Info: Implemented 4 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "139 " "Info: Allocated 139 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 14 22:22:49 2008 " "Info: Processing ended: Thu Aug 14 22:22:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Analysis & Synthesis" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Analysis & Synthesis" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0}