--if,wait,cse,loop語(yǔ)句是用于順序代碼的，因此，他們只能在process,function,proceddure中
--if/case 語(yǔ)句在綜合時(shí)會(huì)產(chǎn)生不必要的優(yōu)先級(jí)解碼電路
--結(jié)構(gòu)：
--- if codition then assignments;
--- elsif codition then assignments;
---....
---else assignments;
---endif;
--------------------------------------------------
--循環(huán)累加的模10計(jì)數(shù)器，輸入信號(hào)只有clk，輸出是位寬為４的信號(hào)digit
--process內(nèi)部使用了變量temp來(lái)實(shí)現(xiàn)存儲(chǔ)４位輸出信號(hào)所需的４個(gè)d觸發(fā)器
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------
entity jishuqi is
 port ( clk: in std_logic;
       digit: out integer range 0 to 9);
end jishuqi;
--------------------------------
architecture jishuqi of jishuqi is
 begin 
   count: process (clk)
       variable temp: integer range 0 to 10;
   begin 
      if (clk 'event and clk = '1')then
         temp :=temp+1;
         if (temp =10) then  temp := 0;
         end if;
      end if;
      digit <= temp;
   end process count;
end jishuqi;
-----------------------------------