module gate_control(
					SW0,SW1,SW2,//當(dāng)SW0為高時(shí)，選擇的量程為999999HZ,此時(shí)輸入的1HZ的時(shí)鐘信號(hào)
					f1hz,f10hz,f100hz,
					Latch_EN,
					Counter_Clr,
					Counter_EN,
					dp_s1hz,dp_s10hz,dp_s100hz
					); 
output Latch_EN;                  //用來使能寄存器鎖存數(shù)據(jù)
output Counter_Clr;               //用于計(jì)數(shù)器清零
output Counter_EN;                //計(jì)數(shù)器開始計(jì)數(shù)
output dp_s1hz,dp_s10hz,dp_s100hz;//小數(shù)點(diǎn)位置顯示控制

input  SW0,SW1,SW2;
input  f1hz,f10hz,f100hz;

reg dp_s1hz,dp_s10hz,dp_s100hz;

reg fref;//頻率門控
reg wire_1;
reg wire_2;

//初始化輸入以及中間量
initial
begin
  fref <= 1'b0;

  wire_1  <= 1'b0;
  wire_2  <= 1'b0;
end


//根據(jù)不同的外界量程選擇，選擇相應(yīng)的計(jì)數(shù)基時(shí)鐘
always @(SW0 or SW1 or SW2 or f1hz or f10hz or f100hz)
begin
  if(SW2 == 1'b1)
    begin
      fref <= f100hz;
      {dp_s1hz,dp_s10hz,dp_s100hz} <= 3'b001;
    end
  else if(SW1 == 1'b1)
    begin
      fref <= f10hz;
      {dp_s1hz,dp_s10hz,dp_s100hz} <= 3'b010;
    end
  else if(SW0 == 1'b1)
    begin
      fref <= f1hz;
      {dp_s1hz,dp_s10hz,dp_s100hz} <= 3'b100;
    end
end


//根據(jù)不同的計(jì)數(shù)基時(shí)鐘，提供輸出相應(yīng)的計(jì)數(shù)器計(jì)數(shù)值的清除脈沖與鎖存器鎖存脈沖
always @(posedge fref) //一個(gè)周期計(jì)數(shù)，一個(gè)周期讀數(shù)據(jù)
begin
  wire_1 <= ! wire_1;//當(dāng)開始計(jì)數(shù)時(shí)wire_1為高，保證Counter_EN為高，下一個(gè)wire_1為高時(shí)，則停止
end

always @(negedge fref)//當(dāng)門控信號(hào)為低時(shí)計(jì)數(shù)完成wire_1為高
begin                 //
    wire_2 <= wire_1;  //加wire_2便于產(chǎn)生跳變沿，且總是在計(jì)數(shù)器期間將值賦給wire_2
end

assign Counter_EN  = wire_1;//在門控信號(hào)為高時(shí)和清零信號(hào)為低時(shí)才計(jì)數(shù)，保證在其的一個(gè)周期內(nèi)計(jì)數(shù)內(nèi)
assign Latch_EN    = (! Counter_EN) & wire_2;//如果不要wire_2則在停止計(jì)數(shù)時(shí)不一定有時(shí)間將數(shù)據(jù)。。。
assign Counter_Clr = (! Counter_EN) & (! Latch_EN) & (! wire_2);
//在上升沿將數(shù)據(jù)送給寄存器。1.計(jì)數(shù)完成，鎖存完成，同時(shí)wire_2為0，即wire_1為0，也即在計(jì)數(shù)時(shí)就
//隨計(jì)數(shù)器清零
endmodule