{ "Info" "ITDB_TSU_RESULT" "fenji:fenji_u5\|out err\[5\] clk 3.144 ns register " "Info: tsu for register \"fenji:fenji_u5\|out\" (data pin = \"err\[5\]\", clock pin = \"clk\") is 3.144 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.541 ns + Longest pin register " "Info: + Longest pin to register delay is 5.541 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.817 ns) 0.817 ns err\[5\] 1 PIN PIN_U9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U9; Fanout = 1; PIN Node = 'err\[5\]'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { err[5] } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.415 ns) + CELL(0.309 ns) 5.541 ns fenji:fenji_u5\|out 2 REG LCFF_X38_Y16_N11 2 " "Info: 2: + IC(4.415 ns) + CELL(0.309 ns) = 5.541 ns; Loc. = LCFF_X38_Y16_N11; Fanout = 2; REG Node = 'fenji:fenji_u5\|out'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.724 ns" { err[5] fenji:fenji_u5|out } "NODE_NAME" } } { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.126 ns ( 20.32 % ) " "Info: Total cell delay = 1.126 ns ( 20.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.415 ns ( 79.68 % ) " "Info: Total interconnect delay = 4.415 ns ( 79.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { err[5] fenji:fenji_u5|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "5.541 ns" { err[5] {} err[5]~combout {} fenji:fenji_u5|out {} } { 0.000ns 0.000ns 4.415ns } { 0.000ns 0.817ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.487 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.487 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 40 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.618 ns) 2.487 ns fenji:fenji_u5\|out 3 REG LCFF_X38_Y16_N11 2 " "Info: 3: + IC(0.672 ns) + CELL(0.618 ns) = 2.487 ns; Loc. = LCFF_X38_Y16_N11; Fanout = 2; REG Node = 'fenji:fenji_u5\|out'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { clk~clkctrl fenji:fenji_u5|out } "NODE_NAME" } } { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.19 % ) " "Info: Total cell delay = 1.472 ns ( 59.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.015 ns ( 40.81 % ) " "Info: Total interconnect delay = 1.015 ns ( 40.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.487 ns" { clk clk~clkctrl fenji:fenji_u5|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.487 ns" { clk {} clk~combout {} clk~clkctrl {} fenji:fenji_u5|out {} } { 0.000ns 0.000ns 0.343ns 0.672ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "5.541 ns" { err[5] fenji:fenji_u5|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "5.541 ns" { err[5] {} err[5]~combout {} fenji:fenji_u5|out {} } { 0.000ns 0.000ns 4.415ns } { 0.000ns 0.817ns 0.309ns } "" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.487 ns" { clk clk~clkctrl fenji:fenji_u5|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.487 ns" { clk {} clk~combout {} clk~clkctrl {} fenji:fenji_u5|out {} } { 0.000ns 0.000ns 0.343ns 0.672ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk2 cnt\[3\] cnt\[3\]~reg0 7.344 ns register " "Info: tco from clock \"clk2\" to destination pin \"cnt\[3\]\" through register \"cnt\[3\]~reg0\" is 7.344 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 2.495 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to source register is 2.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clk2 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clk2~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'clk2~clkctrl'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk2 clk2~clkctrl } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.495 ns cnt\[3\]~reg0 3 REG LCFF_X38_Y19_N3 15 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt\[3\]~reg0'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { clk2~clkctrl cnt[3]~reg0 } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 133 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 59.40 % ) " "Info: Total cell delay = 1.482 ns ( 59.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.60 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk2 clk2~clkctrl cnt[3]~reg0 } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk2 {} clk2~combout {} clk2~clkctrl {} cnt[3]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 133 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.755 ns + Longest register pin " "Info: + Longest register to pin delay is 4.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[3\]~reg0 1 REG LCFF_X38_Y19_N3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt\[3\]~reg0'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[3]~reg0 } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 133 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.783 ns) + CELL(1.972 ns) 4.755 ns cnt\[3\] 2 PIN PIN_W5 0 " "Info: 2: + IC(2.783 ns) + CELL(1.972 ns) = 4.755 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'cnt\[3\]'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.755 ns" { cnt[3]~reg0 cnt[3] } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.972 ns ( 41.47 % ) " "Info: Total cell delay = 1.972 ns ( 41.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.783 ns ( 58.53 % ) " "Info: Total interconnect delay = 2.783 ns ( 58.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.755 ns" { cnt[3]~reg0 cnt[3] } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "4.755 ns" { cnt[3]~reg0 {} cnt[3] {} } { 0.000ns 2.783ns } { 0.000ns 1.972ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.495 ns" { clk2 clk2~clkctrl cnt[3]~reg0 } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.495 ns" { clk2 {} clk2~combout {} clk2~clkctrl {} cnt[3]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.864ns 0.000ns 0.618ns } "" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.755 ns" { cnt[3]~reg0 cnt[3] } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "4.755 ns" { cnt[3]~reg0 {} cnt[3] {} } { 0.000ns 2.783ns } { 0.000ns 1.972ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "fenji:fenji_u0\|out err\[0\] clk -1.831 ns register " "Info: th for register \"fenji:fenji_u0\|out\" (data pin = \"err\[0\]\", clock pin = \"clk\") is -1.831 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.480 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 40 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.665 ns) + CELL(0.618 ns) 2.480 ns fenji:fenji_u0\|out 3 REG LCFF_X39_Y18_N17 2 " "Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X39_Y18_N17; Fanout = 2; REG Node = 'fenji:fenji_u0\|out'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { clk~clkctrl fenji:fenji_u0|out } "NODE_NAME" } } { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.35 % ) " "Info: Total cell delay = 1.472 ns ( 59.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.008 ns ( 40.65 % ) " "Info: Total interconnect delay = 1.008 ns ( 40.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { clk clk~clkctrl fenji:fenji_u0|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { clk {} clk~combout {} clk~clkctrl {} fenji:fenji_u0|out {} } { 0.000ns 0.000ns 0.343ns 0.665ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.460 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.460 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns err\[0\] 1 PIN PIN_K3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_K3; Fanout = 1; PIN Node = 'err\[0\]'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "" { err[0] } "NODE_NAME" } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.442 ns) + CELL(0.053 ns) 4.305 ns fenji:fenji_u0\|out~feeder 2 COMB LCCOMB_X39_Y18_N16 1 " "Info: 2: + IC(3.442 ns) + CELL(0.053 ns) = 4.305 ns; Loc. = LCCOMB_X39_Y18_N16; Fanout = 1; COMB Node = 'fenji:fenji_u0\|out~feeder'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { err[0] fenji:fenji_u0|out~feeder } "NODE_NAME" } } { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.460 ns fenji:fenji_u0\|out 3 REG LCFF_X39_Y18_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.460 ns; Loc. = LCFF_X39_Y18_N17; Fanout = 2; REG Node = 'fenji:fenji_u0\|out'" {  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { fenji:fenji_u0|out~feeder fenji:fenji_u0|out } "NODE_NAME" } } { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.018 ns ( 22.83 % ) " "Info: Total cell delay = 1.018 ns ( 22.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.442 ns ( 77.17 % ) " "Info: Total interconnect delay = 3.442 ns ( 77.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.460 ns" { err[0] fenji:fenji_u0|out~feeder fenji:fenji_u0|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "4.460 ns" { err[0] {} err[0]~combout {} fenji:fenji_u0|out~feeder {} fenji:fenji_u0|out {} } { 0.000ns 0.000ns 3.442ns 0.000ns } { 0.000ns 0.810ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "2.480 ns" { clk clk~clkctrl fenji:fenji_u0|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "2.480 ns" { clk {} clk~combout {} clk~clkctrl {} fenji:fenji_u0|out {} } { 0.000ns 0.000ns 0.343ns 0.665ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/soft_install/altera/quartusii7.2/install/quartus/bin/TimingClosureFloorplan.fld" "" "4.460 ns" { err[0] fenji:fenji_u0|out~feeder fenji:fenji_u0|out } "NODE_NAME" } } { "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/soft_install/altera/quartusii7.2/install/quartus/bin/Technology_Viewer.qrui" "4.460 ns" { err[0] {} err[0]~combout {} fenji:fenji_u0|out~feeder {} fenji:fenji_u0|out {} } { 0.000ns 0.000ns 3.442ns 0.000ns } { 0.000ns 0.810ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}