/* i82527.c * Linux CAN-bus device driver. * Written by Arnaud Westenberg email:arnaud@wanadoo.nl * This software is released under the GPL-License. * Version 0.7  6 Aug 2001 */#define __NO_VERSION__#include <linux/module.h>#include <linux/autoconf.h>#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)#define MODVERSIONS#endif#if defined (MODVERSIONS)#include <linux/modversions.h>#endif#include <linux/fs.h>#include "../include/main.h"#include "../include/i82527.h"extern int stdmask;extern int extmask;extern int mo15mask;int i82527_enable_configuration(struct chip_t *chip){	unsigned short flags=0;	flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);	can_write_reg(chip, flags|iCTL_CCE, iCTL);		return 0;}int i82527_disable_configuration(struct chip_t *chip){	unsigned short flags=0;	flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);	can_write_reg(chip, flags, iCTL);	return 0;}int i82527_chip_config(struct chip_t *chip){	can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface	can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration	can_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates 	can_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */	can_write_reg(chip,0x00,iSTAT); /* Clear error status register */	/* Check if we can at least read back some arbitrary data from the 	 * card. If we can not, the card is not properly configured!	 */	can_write_reg(chip,0x25,MSG_OFFSET(1)+iMSGDAT1);	can_write_reg(chip,0x52,MSG_OFFSET(2)+iMSGDAT3);	can_write_reg(chip,0xc3,MSG_OFFSET(10)+iMSGDAT6);	if ( (can_read_reg(chip,MSG_OFFSET(1)+iMSGDAT1) != 0x25) ||	      (can_read_reg(chip,MSG_OFFSET(2)+iMSGDAT3) != 0x52) ||	      (can_read_reg(chip,MSG_OFFSET(10)+iMSGDAT6) != 0xc3) ) {		CANMSG("Could not read back from the hardware.\n");		CANMSG("This probably means that your hardware is not correctly configured!\n");		return -1;	}	else		DEBUGMSG("Could read back, hardware is probably configured correctly\n");	if (baudrate == 0)		baudrate=1000;	if (i82527_baud_rate(chip,baudrate*1000,chip->clock,0,75,0)) {		CANMSG("Error configuring baud rate\n");		return -ENODEV;	}	if (i82527_standard_mask(chip,0x0000,stdmask)) {		CANMSG("Error configuring standard mask\n");		return -ENODEV;	}	if (i82527_extended_mask(chip,0x00000000,extmask)) {		CANMSG("Error configuring extended mask\n");		return -ENODEV;	}	if (i82527_message15_mask(chip,0x00000000,mo15mask)) {		CANMSG("Error configuring message 15 mask\n");		return -ENODEV;	}	if (i82527_clear_objects(chip)) {		CANMSG("Error clearing message objects\n");		return -ENODEV;	}	if (i82527_config_irqs(chip,0x0a)) {		CANMSG("Error configuring interrupts\n");		return -ENODEV;	}	return 0;}/* Set communication parameters. * param rate baud rate in Hz * param clock frequency of i82527 clock in Hz (ISA osc is 14318000) * param sjw synchronization jump width (0-3) prescaled clock cycles * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP */int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,							int sampl_pt, int flags){	int best_error = 1000000000, error;	int best_tseg=0, best_brp=0, best_rate=0, brp=0;	int tseg=0, tseg1=0, tseg2=0;		if (i82527_enable_configuration(chip))		return -ENODEV;	clock /=2;	/* tseg even = round down, odd = round up */	for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {		brp = clock/((1+tseg/2)*rate)+tseg%2;		if (brp == 0 || brp > 64)			continue;		error = rate - clock/(brp*(1+tseg/2));		if (error < 0)			error = -error;		if (error <= best_error) {			best_error = error;			best_tseg = tseg/2;			best_brp = brp-1;			best_rate = clock/(brp*(1+tseg/2));		}	}	if (best_error && (rate/best_error < 10)) {		CANMSG("baud rate %d is not possible with %d Hz clock\n",								rate, 2*clock);		CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",				best_rate, best_brp, best_tseg, tseg1, tseg2);		return -EINVAL;	}	tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;	if (tseg2 < 0)		tseg2 = 0;	if (tseg2 > MAX_TSEG2)		tseg2 = MAX_TSEG2;		tseg1 = best_tseg-tseg2-2;	if (tseg1>MAX_TSEG1) {		tseg1 = MAX_TSEG1;		tseg2 = best_tseg-tseg1-2;	}	DEBUGMSG("Setting %d bps.\n", best_rate);	DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",					best_brp, best_tseg, tseg1, tseg2,					(100*(best_tseg-tseg2)/(best_tseg+1)));										can_write_reg(chip, sjw<<6 | best_brp, iBT0);	can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,								iBT1);	DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));	DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 | 							tseg2<<4 | tseg1);	i82527_disable_configuration(chip);	return 0;}int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask){	unsigned char mask0, mask1;	mask0 = (unsigned char) (mask >> 3);	mask1 = (unsigned char) (mask << 5);		can_write_reg(chip,mask0,iSGM0);	can_write_reg(chip,mask1,iSGM1);	DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);	return 0;}int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask){	unsigned char mask0, mask1, mask2, mask3;	mask0 = (unsigned char) (mask >> 21);	mask1 = (unsigned char) (mask >> 13);	mask2 = (unsigned char) (mask >> 5);	mask3 = (unsigned char) (mask << 3);	can_write_reg(chip,mask0,iEGM0);	can_write_reg(chip,mask1,iEGM1);	can_write_reg(chip,mask2,iEGM2);	can_write_reg(chip,mask3,iEGM3);	DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);	return 0;}int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask){	unsigned char mask0, mask1, mask2, mask3;	mask0 = (unsigned char) (mask >> 21);	mask1 = (unsigned char) (mask >> 13);	mask2 = (unsigned char) (mask >> 5);	mask3 = (unsigned char) (mask << 3);	can_write_reg(chip,mask0,i15M0);	can_write_reg(chip,mask1,i15M1);	can_write_reg(chip,mask2,i15M2);	can_write_reg(chip,mask3,i15M3);	DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);	return 0;}int i82527_clear_objects(struct chip_t *chip){	int i=0,id=0,data=0;	DEBUGMSG("Cleared all message objects on chip\n");	for (i=1; i<=15; i++) {		can_write_reg(chip,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES) ,							MSG_OFFSET(i)+iMSGCTL0);		can_write_reg(chip,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES) ,							MSG_OFFSET(i)+iMSGCTL1);		for (data=0x07; data<0x0f; data++)			can_write_reg(chip,0x00,MSG_OFFSET(i)+data);		for (id=2; id<6; id++) {			can_write_reg(chip,0x00,MSG_OFFSET(i)+id);		}		if (extended==0) {			can_write_reg(chip,0x00,MSG_OFFSET(i)+iMSGCFG);		}		else {			can_write_reg(chip,MCFG_XTD,MSG_OFFSET(i)+iMSGCFG);		}	}	if (extended==0)		DEBUGMSG("All message ID's set to standard\n");	else		DEBUGMSG("All message ID's set to extended\n");		return 0;}int i82527_config_irqs(struct chip_t *chip, short irqs){	can_write_reg(chip,irqs,iCTL);	DEBUGMSG("Configured hardware interrupt delivery\n");	return 0;}int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj){	if (extended) {		can_write_reg(chip,MCFG_XTD,MSG_OFFSET(obj->object)+iMSGCFG);	}	else {		can_write_reg(chip,0x00,MSG_OFFSET(obj->object)+iMSGCFG);	}	can_write_reg(chip ,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES),					MSG_OFFSET(obj->object)+iMSGCTL1);	can_write_reg(chip ,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),					MSG_OFFSET(obj->object)+iMSGCTL0);		return 0;}int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, 							struct canmsg_t *msg){	int i=0,id0=0,id1=0,id2=0,id3=0;	can_write_reg(chip,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),					MSG_OFFSET(obj->object)+iMSGCTL1);	can_write_reg(chip,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),					MSG_OFFSET(obj->object)+iMSGCTL0);	if (extended) {		can_write_reg(chip,(msg->length<<4)+(MCFG_DIR|MCFG_XTD),					MSG_OFFSET(obj->object)+iMSGCFG);	}	else {		can_write_reg(chip,(msg->length<<4)+MCFG_DIR,					MSG_OFFSET(obj->object)+iMSGCFG);	}	if (extended) {		id0 = (unsigned char) (msg->id<<3);		id1 = (unsigned char) (msg->id>>5);		id2 = (unsigned char) (msg->id>>13);		id3 = (unsigned char) (msg->id>>21);		can_write_reg(chip,id0,MSG_OFFSET(obj->object)+iMSGID3);		can_write_reg(chip,id1,MSG_OFFSET(obj->object)+iMSGID2);		can_write_reg(chip,id2,MSG_OFFSET(obj->object)+iMSGID1);		can_write_reg(chip,id3,MSG_OFFSET(obj->object)+iMSGID0);	}	else {		id1 = (unsigned char) (msg->id<<5);		id0 = (unsigned char) (msg->id>>3);		can_write_reg(chip,id1,MSG_OFFSET(obj->object)+iMSGID1);		can_write_reg(chip,id0,MSG_OFFSET(obj->object)+iMSGID0);	}	can_write_reg(chip,0xfa,MSG_OFFSET(obj->object)+iMSGCTL1);	for (i=0; i<msg->length; i++) {		can_write_reg(chip,msg->data[i],MSG_OFFSET(obj->object)+								iMSGDAT0+i);	}	return 0;}int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,							struct canmsg_t *msg){	if (msg->flags & MSG_RTR) {		can_write_reg(chip,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),					MSG_OFFSET(obj->object)+iMSGCTL1);	}	else {		can_write_reg(chip,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),					MSG_OFFSET(obj->object)+iMSGCTL1);	}	return 0;}int i82527_check_tx_stat(struct chip_t *chip){	if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {		can_write_reg(chip,0x0,iSTAT);		return 0;	}	else {		can_write_reg(chip,0x0,iSTAT);		return 1;	}}int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj){	can_write_reg(chip, (MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES), 					MSG_OFFSET(obj->object)+iMSGCTL0);	can_write_reg(chip, (RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES), 					MSG_OFFSET(obj->object)+iMSGCTL1);		return 0;}int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,							unsigned short btr1){	if (i82527_enable_configuration(chip))		return -ENODEV;	can_write_reg(chip, btr0, iBT0);	can_write_reg(chip, btr1, iBT1);	i82527_disable_configuration(chip);	return 0;}int i82527_start_chip(struct chip_t *chip){	unsigned short flags = 0;	flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);	can_write_reg(chip, flags, iCTL);		return 0;}int i82527_stop_chip(struct chip_t *chip){	unsigned short flags = 0;	flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);	can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);	return 0;}int i82527_register(struct chipspecops_t *chipspecops){	chipspecops->chip_config = i82527_chip_config;	chipspecops->baud_rate = i82527_baud_rate;	chipspecops->standard_mask = i82527_standard_mask;	chipspecops->extended_mask = i82527_extended_mask;	chipspecops->message15_mask = i82527_message15_mask;	chipspecops->clear_objects = i82527_clear_objects;	chipspecops->config_irqs = i82527_config_irqs;	chipspecops->pre_read_config = i82527_pre_read_config;	chipspecops->pre_write_config = i82527_pre_write_config;	chipspecops->send_msg = i82527_send_msg;	chipspecops->check_tx_stat = i82527_check_tx_stat;	chipspecops->remote_request = i82527_remote_request;	chipspecops->enable_configuration = i82527_enable_configuration;	chipspecops->disable_configuration = i82527_disable_configuration;	chipspecops->set_btregs = i82527_set_btregs;	chipspecops->start_chip = i82527_start_chip;	chipspecops->stop_chip = i82527_stop_chip;	return 0;}