+-------+--------------+------------+--------+----+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+--------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To ;
+-------+-------------------+-----------------+--------+----+
; N/A   ; None              ; 8.557 ns        ; orient ; g  ;
; N/A   ; None              ; 8.514 ns        ; orient ; r  ;
; N/A   ; None              ; 8.444 ns        ; orient ; b  ;
+-------+-------------------+-----------------+--------+----+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+--------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To     ; To Clock ;
+---------------+-------------+-----------+--------+--------+----------+
; N/A           ; None        ; -2.579 ns ; orient ; mmd[0] ; clk      ;
; N/A           ; None        ; -2.579 ns ; orient ; mmd[1] ; clk      ;
+---------------+-------------+-----------+--------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Feb 14 20:37:00 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA -c VGA
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "cc[4]" as buffer
    Info: Detected ripple clock "clk_int[1]" as buffer
    Info: Detected ripple clock "fs[2]" as buffer
Info: Clock "clk" has Internal fmax of 121.49 MHz between source register "ll[4]" and destination register "ll[5]" (period= 8.231 ns)
    Info: + Longest register to register delay is 7.522 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y1_N6; Fanout = 8; REG Node = 'll[4]'
        Info: 2: + IC(3.226 ns) + CELL(0.200 ns) = 3.426 ns; Loc. = LC_X4_Y2_N5; Fanout = 5; COMB Node = 'Equal3~65'
        Info: 3: + IC(3.292 ns) + CELL(0.804 ns) = 7.522 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll[5]'
        Info: Total cell delay = 1.004 ns ( 13.35 % )
        Info: Total interconnect delay = 6.518 ns ( 86.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 16.693 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int[1]'
            Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs[2]'
            Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc[4]'
            Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll[5]'
            Info: Total cell delay = 5.963 ns ( 35.72 % )
            Info: Total interconnect delay = 10.730 ns ( 64.28 % )
        Info: - Longest clock path from clock "clk" to source register is 16.693 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int[1]'
            Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs[2]'
            Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc[4]'
            Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X3_Y1_N6; Fanout = 8; REG Node = 'll[4]'
            Info: Total cell delay = 5.963 ns ( 35.72 % )
            Info: Total interconnect delay = 10.730 ns ( 64.28 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "mmd[0]" (data pin = "orient", clock pin = "clk") is 3.133 ns
    Info: + Longest pin to register delay is 6.148 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 5; PIN Node = 'orient'
        Info: 2: + IC(3.773 ns) + CELL(1.243 ns) = 6.148 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd[0]'
        Info: Total cell delay = 2.375 ns ( 38.63 % )
        Info: Total interconnect delay = 3.773 ns ( 61.37 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd[0]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: tco from clock "clk" to destination pin "r" through register "ll[5]" is 27.526 ns
    Info: + Longest clock path from clock "clk" to source register is 16.693 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N3; Fanout = 4; REG Node = 'clk_int[1]'
        Info: 3: + IC(3.516 ns) + CELL(1.294 ns) = 8.534 ns; Loc. = LC_X3_Y3_N2; Fanout = 6; REG Node = 'fs[2]'
        Info: 4: + IC(3.201 ns) + CELL(1.294 ns) = 13.029 ns; Loc. = LC_X2_Y3_N4; Fanout = 15; REG Node = 'cc[4]'
        Info: 5: + IC(2.746 ns) + CELL(0.918 ns) = 16.693 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll[5]'
        Info: Total cell delay = 5.963 ns ( 35.72 % )
        Info: Total interconnect delay = 10.730 ns ( 64.28 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 10.457 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N3; Fanout = 9; REG Node = 'll[5]'
        Info: 2: + IC(1.954 ns) + CELL(0.914 ns) = 2.868 ns; Loc. = LC_X3_Y1_N6; Fanout = 2; COMB Node = 'LessThan14~84'
        Info: 3: + IC(1.204 ns) + CELL(0.511 ns) = 4.583 ns; Loc. = LC_X2_Y1_N0; Fanout = 1; COMB Node = 'grb~2100'
        Info: 4: + IC(0.723 ns) + CELL(0.740 ns) = 6.046 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'grb~2104'
        Info: 5: + IC(2.089 ns) + CELL(2.322 ns) = 10.457 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'r'
        Info: Total cell delay = 4.487 ns ( 42.91 % )
        Info: Total interconnect delay = 5.970 ns ( 57.09 % )
Info: Longest tpd from source pin "orient" to destination pin "g" is 8.557 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 5; PIN Node = 'orient'
    Info: 2: + IC(2.367 ns) + CELL(0.740 ns) = 4.239 ns; Loc. = LC_X2_Y1_N2; Fanout = 1; COMB Node = 'grb~2107'
    Info: 3: + IC(1.996 ns) + CELL(2.322 ns) = 8.557 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'g'
    Info: Total cell delay = 4.194 ns ( 49.01 % )
    Info: Total interconnect delay = 4.363 ns ( 50.99 % )
Info: th for register "mmd[0]" (data pin = "orient", clock pin = "clk") is -2.579 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd[0]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 6.148 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 5; PIN Node = 'orient'
        Info: 2: + IC(3.773 ns) + CELL(1.243 ns) = 6.148 ns; Loc. = LC_X2_Y2_N9; Fanout = 7; REG Node = 'mmd[0]'
        Info: Total cell delay = 2.375 ns ( 38.63 % )
        Info: Total interconnect delay = 3.773 ns ( 61.37 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Feb 14 20:37:01 2009
    Info: Elapsed time: 00:00:02