# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = FalseSET verilogsim = TrueSET workingdirectory = C:\my_projec\firewallSET speedgrade = -7SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc2vp30SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff896SET createndf = FalseSET designentry = VerilogSET devicefamily = virtex2pSET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Dual_Port_Block_Memory family Xilinx,_Inc. 6.3# END Select# BEGIN ParametersCSET port_a_init_value=0CSET port_b_init_pin=falseCSET port_b_enable_pin_polarity=Active_HighCSET port_a_additional_output_pipe_stages=0CSET port_b_initialization_pin_polarity=Active_HighCSET select_primitive=16kx1CSET port_a_init_pin=falseCSET port_b_active_clock_edge=Rising_Edge_TriggeredCSET port_a_handshaking_pins=falseCSET global_init_value=0CSET port_a_enable_pin_polarity=Active_HighCSET port_b_init_value=0CSET depth_a=256CSET depth_b=256CSET port_a_write_enable_polarity=Active_HighCSET component_name=dpram256x80CSET disable_warning_messages=trueCSET port_a_enable_pin=falseCSET configuration_port_a=Write_OnlyCSET write_mode_port_a=Read_After_WriteCSET configuration_port_b=Read_OnlyCSET write_mode_port_b=Read_After_WriteCSET port_b_register_inputs=falseCSET primitive_selection=Optimize_For_AreaCSET width_a=80CSET width_b=80CSET port_a_active_clock_edge=Rising_Edge_TriggeredCSET port_b_additional_output_pipe_stages=0CSET port_b_write_enable_polarity=Active_HighCSET load_init_file=falseCSET port_a_register_inputs=falseCSET port_a_initialization_pin_polarity=Active_HighCSET port_b_handshaking_pins=falseCSET port_b_enable_pin=true# END ParametersGENERATE