# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = FalseSET verilogsim = TrueSET workingdirectory = C:\my_projec\firewallSET speedgrade = -7SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc2vp30SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff896SET createndf = FalseSET designentry = VerilogSET devicefamily = virtex2pSET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Content_Addressable_Memory family Xilinx,_Inc. 5.1# END Select# BEGIN ParametersCSET read_warning_flag=falseCSET address_resolution=lowestCSET memory_type=srl16eCSET match_address_type=binary_encodedCSET depth=256CSET data_width=32CSET multiple_match_flag=falseCSET register_outputs=falseCSET ternary_mode=ternary_mode_standardCSET enable=trueCSET component_name=camCSET read_only_cam=falseCSET simultaneous_read_write=trueCSET single_match_flag=falseCSET load_initialization_file=false# END ParametersGENERATE