//
//-----------------------------------------------------------------------------
// Title      : 
// Project    : 
//-----------------------------------------------------------------------------
// File       : conf_if.v
// Author     : 
// Date       : 07-11-1
//-----------------------------------------------------------------------------
// Description: 
//
//-----------------------------------------------------------------------------

`timescale 1ns/10ps

module conf_if(
sys_clk,
sys_rst_n,
ppc_ce_n_conf,
ppc_we_n_conf,
ppc_re_n_conf,
ppc_clr_n_conf,
ppc_addr_conf,
ppc_wdat_conf,
conf_rdat_ppc,
conf_wr_cal,   
conf_rd_cal,    
conf_clr_cal,   
cal_rdat_conf,
conf_wr_ci,
conf_rd_ci,
conf_clr_ci,
ci_rdat_conf,
conf_wr_drop,   
conf_rd_drop,    
conf_clr_drop,
drop_rdat_conf,
conf_wr_fs,
conf_rd_fs,
conf_clr_fs,
fs_rdat_conf,
conf_wr_mac,
conf_rd_mac,
conf_clr_mac,
mac_rdat_conf,
conf_wdat,
conf_addr
);


/*-------------------------------------------------------------------*\
                          Parameter Description
\*-------------------------------------------------------------------*/
parameter D = 2;

/*-------------------------------------------------------------------*\
                            Port Description
\*-------------------------------------------------------------------*/ 

//   Global Signals
input		            sys_clk;
input		            sys_rst_n;
                    
input               ppc_ce_n_conf;    //ppc  chip enable signal to conf
input               ppc_we_n_conf;    //ppc  write enable signal to conf
input               ppc_re_n_conf;    //ppc  read enable signal to conf
input               ppc_clr_n_conf;   //ppc  clear singal to conf
input  [7:0]        ppc_addr_conf;    //ppc  write address to conf
input  [15:0]       ppc_wdat_conf;    //ppc  write data to conf
output [15:0]       conf_rdat_ppc;    //conf read data to ppc

//interface with len_cal
output              conf_wr_cal;     
output              conf_rd_cal;    
output              conf_clr_cal;   
input   [15:0]      cal_rdat_conf;

output              conf_wr_ci;
output              conf_rd_ci;
output              conf_clr_ci;
input    [15:0]     ci_rdat_conf;

output              conf_wr_drop;   
output              conf_rd_drop;    
output              conf_clr_drop;   
input    [15:0]     drop_rdat_conf;

output              conf_wr_fs;   
output              conf_rd_fs;    
output              conf_clr_fs;   
input    [15:0]     fs_rdat_conf;

output              conf_wr_mac;   
output              conf_rd_mac;    
output              conf_clr_mac;   
input    [15:0]     mac_rdat_conf;

output   [15:0]     conf_wdat;
output   [3:0]      conf_addr;
/*-------------------------------------------------------------------*\
                          Reg/Wire Description
\*-------------------------------------------------------------------*/
reg              f1_ppc_ce_n;
reg              f1_ppc_we_n; 
reg              f1_ppc_re_n; 
reg              f1_ppc_clr_n;
reg  [7:0]       f1_ppc_addr; 
reg  [15:0]      f1_ppc_wdat; 
reg              f2_ppc_ce_n;
reg              f2_ppc_we_n; 
reg              f2_ppc_re_n; 
reg              f2_ppc_clr_n;
reg  [7:0]       f2_ppc_addr; 
reg  [15:0]      f2_ppc_wdat; 
wire             wr_en_tmp0;
reg              wr_en_tmp1;
wire             write_op;
reg              conf_wr_cal;
reg              conf_wr_ci;
reg              conf_wr_drop;
reg              conf_wr_fs; 
reg              conf_wr_mac; 
reg  [3:0]       conf_addr;
reg  [15:0]      conf_wdat;
reg              clear_tmp0;
reg              clear_tmp1;
reg              clear_op;
reg  [7:0]       clear_addr;
reg              conf_clr_cal;
reg              conf_clr_ci;
reg              conf_clr_drop; 
reg              conf_clr_fs;  
reg              conf_clr_mac;
wire             rd_en_tmp0;
reg              rd_en_tmp1;
wire             read_op;
reg              conf_rd_cal;
reg              conf_rd_ci;
reg              conf_rd_drop;
reg              conf_rd_fs;
reg              conf_rd_mac;
reg              f1_read_op;
reg              f2_read_op;
reg              f3_read_op;
reg              f4_read_op;
reg   [15:0]     conf_rdat_ppc;
/*-------------------------------------------------------------------*\
                               Main Codes
\*-------------------------------------------------------------------*/

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
    begin
        f1_ppc_ce_n  <= #D 1'b1;
        f1_ppc_we_n  <= #D 1'b1;
        f1_ppc_re_n  <= #D 1'b0;
        f1_ppc_clr_n <= #D 1'b1;
        f1_ppc_addr  <= #D 8'b0;
        f1_ppc_wdat  <= #D 16'b0;
    end
    else
    begin
        f1_ppc_ce_n  <= #D ppc_ce_n_conf;
        f1_ppc_we_n  <= #D ppc_we_n_conf;
        f1_ppc_re_n  <= #D ppc_re_n_conf;
        f1_ppc_clr_n <= #D ppc_clr_n_conf;
        f1_ppc_addr  <= #D ppc_addr_conf;
        f1_ppc_wdat  <= #D ppc_wdat_conf;
    end
end

always @( posedge sys_clk or negedge sys_rst_n)
begin
    if( !sys_rst_n )
    begin
        f2_ppc_ce_n  <= #D 1'b1;
        f2_ppc_we_n  <= #D 1'b1;
        f2_ppc_re_n  <= #D 1'b0;
        f2_ppc_clr_n <= #D 1'b1;
        f2_ppc_addr  <= #D 8'b0;
        f2_ppc_wdat  <= #D 16'b0;
    end
    else
    begin
        f2_ppc_ce_n  <= #D f1_ppc_ce_n;
        f2_ppc_we_n  <= #D f1_ppc_we_n;
        f2_ppc_re_n  <= #D f1_ppc_re_n;
        f2_ppc_clr_n <= #D f1_ppc_clr_n;
        f2_ppc_addr  <= #D f1_ppc_addr;
        f2_ppc_wdat  <= #D f1_ppc_wdat;
    end   
end

/*---------------------------------------------*\
                Write Operation
\*---------------------------------------------*/

assign  wr_en_tmp0 = ~f2_ppc_ce_n && ~f2_ppc_we_n;

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        wr_en_tmp1 <= #D 1'b0;
    else
        wr_en_tmp1 <= #D wr_en_tmp0;
end

assign  write_op = wr_en_tmp0 && ~wr_en_tmp1;

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
    begin 
        conf_wr_cal   <= #D 1'b0;
        conf_wr_ci    <= #D 1'b0;
        conf_wr_drop  <= #D 1'b0;
        conf_wr_fs    <= #D 1'b0;
        conf_wr_mac   <= #D 1'b0;
    end
    else
    begin
        conf_wr_cal   <= #D write_op && f2_ppc_addr[7:4]==4'h0;
        conf_wr_ci    <= #D write_op && f2_ppc_addr[7:4]==4'h1;
        conf_wr_drop  <= #D write_op && f2_ppc_addr[7:4]==4'h2;
        conf_wr_fs    <= #D write_op && f2_ppc_addr[7:4]==4'h3;
        conf_wr_mac   <= #D write_op && f2_ppc_addr[7:4]==4'h4;
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        conf_addr <= #D 4'b0;
    else if( read_op || write_op )
        conf_addr <= #D f2_ppc_addr[3:0];
    else if( clear_op )
        conf_addr <= #D clear_addr[3:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        conf_wdat <= #D 15'b0;
    else if( write_op )
        conf_wdat <= #D f2_ppc_wdat[15:0];
end

/*---------------------------------------------*\
                      Clear 
\*---------------------------------------------*/ 

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
    begin
        clear_tmp0 <= #D 1'b0;
        clear_tmp1 <= #D 1'b0;
    end
    else
    begin
        clear_tmp0 <= #D ~f2_ppc_clr_n && ~f2_ppc_ce_n;
        clear_tmp1 <= #D clear_tmp0;
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        clear_op <= #D 1'b0;
    else if( clear_tmp0 && ~clear_tmp1 )
        clear_op <= #D 1'b1;
    else
        clear_op <= #D 1'b0;
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        clear_addr[7:0] <= #D 8'b0;
    else if( clear_tmp0 && ~clear_tmp1)
        clear_addr[7:0] <= #D f2_ppc_wdat[7:0];
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
    begin 
        conf_clr_cal   <= #D 1'b0;
        conf_clr_ci    <= #D 1'b0;
        conf_clr_drop  <= #D 1'b0;
        conf_clr_fs    <= #D 1'b0;
        conf_clr_mac   <= #D 1'b0;
    end
    else
    begin
        conf_clr_cal   <= #D clear_op && clear_addr[7:4]==4'h0;
        conf_clr_ci    <= #D clear_op && clear_addr[7:4]==4'h1;
        conf_clr_drop  <= #D clear_op && clear_addr[7:4]==4'h2;
        conf_clr_fs    <= #D clear_op && clear_addr[7:4]==4'h3;
        conf_clr_mac   <= #D clear_op && clear_addr[7:4]==4'h4;
    end
end

/*---------------------------------------------*\
                 Read Operation
\*---------------------------------------------*/ 

assign  rd_en_tmp0 = ~f2_ppc_ce_n && ~f2_ppc_re_n;

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        rd_en_tmp1 <= #D 1'b0;
    else
        rd_en_tmp1 <= #D rd_en_tmp0;
end

assign  read_op = rd_en_tmp0 && ~rd_en_tmp1;

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n )
    begin 
        conf_rd_cal   <= #D 1'b0;
        conf_rd_ci    <= #D 1'b0;
        conf_rd_drop  <= #D 1'b0;
        conf_rd_fs    <= #D 1'b0;
        conf_rd_mac   <= #D 1'b0;
    end
    else
    begin
        conf_rd_cal   <= #D read_op && f2_ppc_addr[7:4]==4'h0;
        conf_rd_ci    <= #D read_op && f2_ppc_addr[7:4]==4'h1;
        conf_rd_drop  <= #D read_op && f2_ppc_addr[7:4]==4'h2;
        conf_rd_fs    <= #D read_op && f2_ppc_addr[7:4]==4'h3;
        conf_rd_mac   <= #D read_op && f2_ppc_addr[7:4]==4'h4;
    end
end                      
                    
always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
    begin
        f1_read_op <= #D 1'b0;
        f2_read_op <= #D 1'b0;
        f3_read_op <= #D 1'b0;
        f4_read_op <= #D 1'b0;
    end
    else
    begin
        f1_read_op <= #D read_op;
        f2_read_op <= #D f1_read_op;
        f3_read_op <= #D f2_read_op;
        f4_read_op <= #D f3_read_op;
    end
end

always @( posedge sys_clk or negedge sys_rst_n )
begin
    if( !sys_rst_n ) 
        conf_rdat_ppc <= #D 16'b0;
    else if( f4_read_op )
    begin
        case( f2_ppc_addr[7:4] )
        4'h0   : conf_rdat_ppc <= #D cal_rdat_conf;
        4'h1   : conf_rdat_ppc <= #D ci_rdat_conf;
        4'h2   : conf_rdat_ppc <= #D drop_rdat_conf;
        4'h3   : conf_rdat_ppc <= #D fs_rdat_conf;
        4'h4   : conf_rdat_ppc <= #D mac_rdat_conf;
        default: conf_rdat_ppc <= #D 16'b0;
        endcase
    end
end

endmodule