NewProject(C:/myprojec1/pcores/myfirewall_v1_00_a/devl/projnav/myfirewall.ise)
SetProperty(Device Family, virtex2p)
SetProperty(Device, xc2vp7)
SetProperty(Package, fg456)
SetProperty(Speed Grade, -6)
SetProperty(Top-Level Module Type, HDL)
SetProperty(Synthesis Tool, XST (VHDL/Verilog))
SetProperty(Simulator, Modelsim-SE Mixed)
SetPreference(PathType, Absolute)
AddLibrary(myfirewall_v1_00_a, C:/myprojec1/pcores, TRUE)
AddSource(C:/myprojec1/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd, VHDL Module)
MoveToLibrary(C:/myprojec1/pcores/myfirewall_v1_00_a/hdl/vhdl/myfirewall.vhd, myfirewall_v1_00_a)
AddSource(C:/myprojec1/pcores/myfirewall_v1_00_a/hdl/verilog/user_logic.v, Verilog Module)
AddLibrary(proc_common_v2_00_a, g:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common_pkg.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lut4.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_bit.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_top.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_counter_top.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bit.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_select.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_reg.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counter.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.vhd, proc_common_v2_00_a)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path_cntr_ai.vhd, proc_common_v2_00_a)
AddLibrary(interrupt_control_v1_00_a, g:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/interrupt_control.vhd, interrupt_control_v1_00_a)
AddLibrary(wrpfifo_v1_01_b, g:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd, wrpfifo_v1_01_b)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr.vhd, wrpfifo_v1_01_b)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl.vhd, wrpfifo_v1_01_b)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd, wrpfifo_v1_01_b)
AddLibrary(rdpfifo_v1_01_b, g:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd.vhd, rdpfifo_v1_01_b)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl.vhd, rdpfifo_v1_01_b)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd, rdpfifo_v1_01_b)
AddLibrary(opb_ipif_v3_01_c, g:/EDK/hw/XilinxProcessorIPLib/pcores, TRUE)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/reset_mir.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_flex_addr_cntr.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/brst_addr_cntr_reg.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_be_gen.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/srl_fifo3.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/write_buffer.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_bam.vhd, opb_ipif_v3_01_c)
AddSource(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, VHDL Module)
MoveToLibrary(g:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_c/hdl/vhdl/opb_ipif.vhd, opb_ipif_v3_01_c)
CloseProject()