//-----------------------------------------------------------------------------
// system.v
//-----------------------------------------------------------------------------

module system
  (
    fpga_0_RS232_Uart_1_RX_pin,
    fpga_0_RS232_Uart_1_TX_pin,
    fpga_0_LEDs_4Bit_GPIO_IO_pin,
    fpga_0_DIPSWs_4Bit_GPIO_IO_pin,
    fpga_0_PushButtons_5Bit_GPIO_IO_pin,
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin,
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin,
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin,
    fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin,
    fpga_0_net_gnd_pin,
    fpga_0_net_gnd_1_pin,
    fpga_0_net_gnd_2_pin,
    fpga_0_net_gnd_3_pin,
    fpga_0_net_gnd_4_pin,
    fpga_0_net_gnd_5_pin,
    fpga_0_net_gnd_6_pin,
    sys_clk_pin,
    sys_rst_pin,
    myfirewall_0_ppc_ce_n_conf_pin,
    myfirewall_0_ppc_we_n_conf_pin,
    myfirewall_0_ppc_re_n_conf_pin,
    myfirewall_0_ppc_clr_n_conf_pin,
    myfirewall_0_ppc_addr_conf_pin,
    myfirewall_0_ppc_wdat_conf_pin,
    myfirewall_0_conf_rdat_ppc_pin
  );
  input fpga_0_RS232_Uart_1_RX_pin;
  output fpga_0_RS232_Uart_1_TX_pin;
  inout [0:3] fpga_0_LEDs_4Bit_GPIO_IO_pin;
  inout [0:3] fpga_0_DIPSWs_4Bit_GPIO_IO_pin;
  inout [0:4] fpga_0_PushButtons_5Bit_GPIO_IO_pin;
  inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin;
  inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin;
  inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin;
  inout fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin;
  output fpga_0_net_gnd_pin;
  output fpga_0_net_gnd_1_pin;
  output fpga_0_net_gnd_2_pin;
  output fpga_0_net_gnd_3_pin;
  output fpga_0_net_gnd_4_pin;
  output fpga_0_net_gnd_5_pin;
  output fpga_0_net_gnd_6_pin;
  input sys_clk_pin;
  input sys_rst_pin;
  output myfirewall_0_ppc_ce_n_conf_pin;
  output myfirewall_0_ppc_we_n_conf_pin;
  output myfirewall_0_ppc_re_n_conf_pin;
  output myfirewall_0_ppc_clr_n_conf_pin;
  output [0:7] myfirewall_0_ppc_addr_conf_pin;
  output [0:15] myfirewall_0_ppc_wdat_conf_pin;
  input [0:15] myfirewall_0_conf_rdat_ppc_pin;

  // Internal signals

  wire C405RSTCHIPRESETREQ;
  wire C405RSTCORERESETREQ;
  wire C405RSTSYSRESETREQ;
  wire PS2_Ports_Clkin1_PS2_Ports_IO_ADAPTER_ps2_clk_rx_1;
  wire PS2_Ports_Clkin2_PS2_Ports_IO_ADAPTER_ps2_clk_rx_2;
  wire PS2_Ports_Clkpd1_PS2_Ports_IO_ADAPTER_ps2_clk_tx_1;
  wire PS2_Ports_Clkpd2_PS2_Ports_IO_ADAPTER_ps2_clk_tx_2;
  wire PS2_Ports_IO_ADAPTER_ps2_d_rx_1_PS2_Ports_Rx1;
  wire PS2_Ports_IO_ADAPTER_ps2_d_rx_2_PS2_Ports_Rx2;
  wire PS2_Ports_IO_ADAPTER_ps2_d_tx_1_PS2_Ports_Txpd1;
  wire PS2_Ports_IO_ADAPTER_ps2_d_tx_2_PS2_Ports_Txpd2;
  wire RSTC405RESETCHIP;
  wire RSTC405RESETCORE;
  wire RSTC405RESETSYS;
  wire dcm_0_lock;
  wire dcm_clk_s;
  wire [0:3] fpga_0_DIPSWs_4Bit_GPIO_IO_I;
  wire [0:3] fpga_0_DIPSWs_4Bit_GPIO_IO_O;
  wire [0:3] fpga_0_DIPSWs_4Bit_GPIO_IO_T;
  wire [0:3] fpga_0_LEDs_4Bit_GPIO_IO_I;
  wire [0:3] fpga_0_LEDs_4Bit_GPIO_IO_O;
  wire [0:3] fpga_0_LEDs_4Bit_GPIO_IO_T;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_I;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_O;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_T;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_I;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_O;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_T;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_I;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_O;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_T;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_I;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_O;
  wire fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_T;
  wire [0:4] fpga_0_PushButtons_5Bit_GPIO_IO_I;
  wire [0:4] fpga_0_PushButtons_5Bit_GPIO_IO_O;
  wire [0:4] fpga_0_PushButtons_5Bit_GPIO_IO_T;
  wire fpga_0_RS232_Uart_1_RX;
  wire fpga_0_RS232_Uart_1_TX;
  wire [0:15] myfirewall_0_conf_rdat_ppc;
  wire [0:7] myfirewall_0_ppc_addr_conf;
  wire myfirewall_0_ppc_ce_n_conf;
  wire myfirewall_0_ppc_clr_n_conf;
  wire myfirewall_0_ppc_re_n_conf;
  wire [0:15] myfirewall_0_ppc_wdat_conf;
  wire myfirewall_0_ppc_we_n_conf;
  wire net_gnd0;
  wire [0:0] net_gnd1;
  wire [0:3] net_gnd4;
  wire [0:4] net_gnd5;
  wire [0:5] net_gnd6;
  wire [0:7] net_gnd8;
  wire [0:9] net_gnd10;
  wire [0:31] net_gnd32;
  wire [0:63] net_gnd64;
  wire net_vcc0;
  wire [0:0] net_vcc1;
  wire [0:5] net_vcc6;
  wire [0:31] opb_M_ABus;
  wire [0:3] opb_M_BE;
  wire [0:31] opb_M_DBus;
  wire [0:0] opb_M_RNW;
  wire [0:0] opb_M_busLock;
  wire [0:0] opb_M_request;
  wire [0:0] opb_M_select;
  wire [0:0] opb_M_seqAddr;
  wire [0:31] opb_OPB_ABus;
  wire [0:3] opb_OPB_BE;
  wire [0:31] opb_OPB_DBus;
  wire [0:0] opb_OPB_MGrant;
  wire opb_OPB_RNW;
  wire opb_OPB_Rst;
  wire opb_OPB_errAck;
  wire opb_OPB_retry;
  wire opb_OPB_select;
  wire opb_OPB_seqAddr;
  wire opb_OPB_timeout;
  wire opb_OPB_xferAck;
  wire [0:191] opb_Sl_DBus;
  wire [0:5] opb_Sl_errAck;
  wire [0:5] opb_Sl_retry;
  wire [0:5] opb_Sl_toutSup;
  wire [0:5] opb_Sl_xferAck;
  wire [0:63] plb_M_ABus;
  wire [0:15] plb_M_BE;
  wire [0:3] plb_M_MSize;
  wire [0:1] plb_M_RNW;
  wire [0:1] plb_M_abort;
  wire [0:1] plb_M_busLock;
  wire [0:1] plb_M_compress;
  wire [0:1] plb_M_guarded;
  wire [0:1] plb_M_lockErr;
  wire [0:1] plb_M_ordered;
  wire [0:3] plb_M_priority;
  wire [0:1] plb_M_rdBurst;
  wire [0:1] plb_M_request;
  wire [0:7] plb_M_size;
  wire [0:5] plb_M_type;
  wire [0:1] plb_M_wrBurst;
  wire [0:127] plb_M_wrDBus;
  wire [0:1] plb_PLB2OPB_rearb;
  wire [0:31] plb_PLB_ABus;
  wire [0:7] plb_PLB_BE;
  wire [0:1] plb_PLB_MAddrAck;
  wire [0:1] plb_PLB_MBusy;
  wire [0:1] plb_PLB_MErr;
  wire [0:1] plb_PLB_MRdBTerm;
  wire [0:1] plb_PLB_MRdDAck;
  wire [0:127] plb_PLB_MRdDBus;
  wire [0:7] plb_PLB_MRdWdAddr;
  wire [0:1] plb_PLB_MRearbitrate;
  wire [0:3] plb_PLB_MSSize;
  wire [0:1] plb_PLB_MSize;
  wire [0:1] plb_PLB_MWrBTerm;
  wire [0:1] plb_PLB_MWrDAck;
  wire plb_PLB_PAValid;
  wire plb_PLB_RNW;
  wire plb_PLB_Rst;
  wire plb_PLB_SAValid;
  wire [0:1] plb_PLB_SMBusy;
  wire [0:1] plb_PLB_SMErr;
  wire plb_PLB_abort;
  wire plb_PLB_busLock;
  wire plb_PLB_compress;
  wire plb_PLB_guarded;
  wire plb_PLB_lockErr;
  wire [0:0] plb_PLB_masterID;
  wire plb_PLB_ordered;
  wire [0:1] plb_PLB_pendPri;
  wire plb_PLB_pendReq;
  wire plb_PLB_rdBurst;
  wire plb_PLB_rdPrim;
  wire [0:1] plb_PLB_reqPri;
  wire [0:3] plb_PLB_size;
  wire [0:2] plb_PLB_type;
  wire plb_PLB_wrBurst;
  wire [0:63] plb_PLB_wrDBus;
  wire plb_PLB_wrPrim;
  wire [0:3] plb_Sl_MBusy;
  wire [0:3] plb_Sl_MErr;
  wire [0:3] plb_Sl_SSize;
  wire [0:1] plb_Sl_addrAck;
  wire [0:1] plb_Sl_rdBTerm;
  wire [0:1] plb_Sl_rdComp;
  wire [0:1] plb_Sl_rdDAck;
  wire [0:127] plb_Sl_rdDBus;
  wire [0:7] plb_Sl_rdWdAddr;
  wire [0:1] plb_Sl_rearbitrate;
  wire [0:1] plb_Sl_wait;
  wire [0:1] plb_Sl_wrBTerm;
  wire [0:1] plb_Sl_wrComp;
  wire [0:1] plb_Sl_wrDAck;
  wire [0:31] plb_bram_if_cntlr_1_port_BRAM_Addr;
  wire plb_bram_if_cntlr_1_port_BRAM_Clk;
  wire [0:63] plb_bram_if_cntlr_1_port_BRAM_Din;
  wire [0:63] plb_bram_if_cntlr_1_port_BRAM_Dout;
  wire plb_bram_if_cntlr_1_port_BRAM_EN;
  wire plb_bram_if_cntlr_1_port_BRAM_Rst;
  wire [0:7] plb_bram_if_cntlr_1_port_BRAM_WEN;
  wire [0:0] sys_bus_reset;
  wire sys_clk_s;
  wire sys_rst_s;

  // Internal assignments

  assign fpga_0_RS232_Uart_1_RX = fpga_0_RS232_Uart_1_RX_pin;
  assign fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX;
  assign dcm_clk_s = sys_clk_pin;
  assign sys_rst_s = sys_rst_pin;
  assign myfirewall_0_ppc_ce_n_conf_pin = myfirewall_0_ppc_ce_n_conf;
  assign myfirewall_0_ppc_we_n_conf_pin = myfirewall_0_ppc_we_n_conf;
  assign myfirewall_0_ppc_re_n_conf_pin = myfirewall_0_ppc_re_n_conf;
  assign myfirewall_0_ppc_clr_n_conf_pin = myfirewall_0_ppc_clr_n_conf;
  assign myfirewall_0_ppc_addr_conf_pin = myfirewall_0_ppc_addr_conf;
  assign myfirewall_0_ppc_wdat_conf_pin = myfirewall_0_ppc_wdat_conf;
  assign myfirewall_0_conf_rdat_ppc = myfirewall_0_conf_rdat_ppc_pin;
  assign plb_PLB2OPB_rearb[1:1] = 1'b0;
  assign net_gnd0 = 1'b0;
  assign fpga_0_net_gnd_pin = net_gnd0;
  assign fpga_0_net_gnd_1_pin = net_gnd0;
  assign fpga_0_net_gnd_2_pin = net_gnd0;
  assign fpga_0_net_gnd_3_pin = net_gnd0;
  assign fpga_0_net_gnd_4_pin = net_gnd0;
  assign fpga_0_net_gnd_5_pin = net_gnd0;
  assign fpga_0_net_gnd_6_pin = net_gnd0;
  assign net_gnd1[0:0] = 1'b0;
  assign net_gnd10[0:9] = 10'b0000000000;
  assign net_gnd32[0:31] = 32'b00000000000000000000000000000000;
  assign net_gnd4[0:3] = 4'b0000;
  assign net_gnd5[0:4] = 5'b00000;
  assign net_gnd6[0:5] = 6'b000000;
  assign net_gnd64[0:63] = 64'b0000000000000000000000000000000000000000000000000000000000000000;
  assign net_gnd8[0:7] = 8'b00000000;
  assign net_vcc0 = 1'b1;
  assign net_vcc1[0:0] = 1'b1;
  assign net_vcc6[0:5] = 6'b111111;

  ppc405_0_wrapper
    ppc405_0 (
      .C405CPMCORESLEEPREQ (  ),
      .C405CPMMSRCE (  ),
      .C405CPMMSREE (  ),
      .C405CPMTIMERIRQ (  ),
      .C405CPMTIMERRESETREQ (  ),
      .C405XXXMACHINECHECK (  ),
      .CPMC405CLOCK ( sys_clk_s ),
      .CPMC405CORECLKINACTIVE ( net_gnd0 ),
      .CPMC405CPUCLKEN ( net_vcc0 ),
      .CPMC405JTAGCLKEN ( net_vcc0 ),
      .CPMC405TIMERCLKEN ( net_vcc0 ),
      .CPMC405TIMERTICK ( net_vcc0 ),
      .MCBCPUCLKEN ( net_vcc0 ),
      .MCBTIMEREN ( net_vcc0 ),
      .MCPPCRST ( net_vcc0 ),
      .PLBCLK ( sys_clk_s ),
      .DCRCLK ( net_gnd0 ),
      .C405RSTCHIPRESETREQ ( C405RSTCHIPRESETREQ ),
      .C405RSTCORERESETREQ ( C405RSTCORERESETREQ ),
      .C405RSTSYSRESETREQ ( C405RSTSYSRESETREQ ),
      .RSTC405RESETCHIP ( RSTC405RESETCHIP ),
      .RSTC405RESETCORE ( RSTC405RESETCORE ),
      .RSTC405RESETSYS ( RSTC405RESETSYS ),
      .C405PLBICUABUS ( plb_M_ABus[32:63] ),
      .C405PLBICUBE ( plb_M_BE[8:15] ),
      .C405PLBICURNW ( plb_M_RNW[1] ),
      .C405PLBICUABORT ( plb_M_abort[1] ),
      .C405PLBICUBUSLOCK ( plb_M_busLock[1] ),
      .C405PLBICUU0ATTR ( plb_M_compress[1] ),
      .C405PLBICUGUARDED ( plb_M_guarded[1] ),
      .C405PLBICULOCKERR ( plb_M_lockErr[1] ),
      .C405PLBICUMSIZE ( plb_M_MSize[2:3] ),
      .C405PLBICUORDERED ( plb_M_ordered[1] ),
      .C405PLBICUPRIORITY ( plb_M_priority[2:3] ),
      .C405PLBICURDBURST ( plb_M_rdBurst[1] ),
      .C405PLBICUREQUEST ( plb_M_request[1] ),
      .C405PLBICUSIZE ( plb_M_size[4:7] ),
      .C405PLBICUTYPE ( plb_M_type[3:5] ),
      .C405PLBICUWRBURST ( plb_M_wrBurst[1] ),
      .C405PLBICUWRDBUS ( plb_M_wrDBus[64:127] ),
      .C405PLBICUCACHEABLE (  ),
      .PLBC405ICUADDRACK ( plb_PLB_MAddrAck[1] ),
      .PLBC405ICUBUSY ( plb_PLB_MBusy[1] ),
      .PLBC405ICUERR ( plb_PLB_MErr[1] ),
      .PLBC405ICURDBTERM ( plb_PLB_MRdBTerm[1] ),
      .PLBC405ICURDDACK ( plb_PLB_MRdDAck[1] ),
      .PLBC405ICURDDBUS ( plb_PLB_MRdDBus[64:127] ),
      .PLBC405ICURDWDADDR ( plb_PLB_MRdWdAddr[4:7] ),
      .PLBC405ICUREARBITRATE ( plb_PLB_MRearbitrate[1] ),
      .PLBC405ICUWRBTERM ( plb_PLB_MWrBTerm[1] ),
      .PLBC405ICUWRDACK ( plb_PLB_MWrDAck[1] ),
      .PLBC405ICUSSIZE ( plb_PLB_MSSize[2:3] ),
      .PLBC405ICUSERR ( plb_PLB_SMErr[1] ),
      .PLBC405ICUSBUSYS ( plb_PLB_SMBusy[1] ),
      .C405PLBDCUABUS ( plb_M_ABus[0:31] ),
      .C405PLBDCUBE ( plb_M_BE[0:7] ),
      .C405PLBDCURNW ( plb_M_RNW[0] ),
      .C405PLBDCUABORT ( plb_M_abort[0] ),
      .C405PLBDCUBUSLOCK ( plb_M_busLock[0] ),
      .C405PLBDCUU0ATTR ( plb_M_compress[0] ),
      .C405PLBDCUGUARDED ( plb_M_guarded[0] ),
      .C405PLBDCULOCKERR ( plb_M_lockErr[0] ),
      .C405PLBDCUMSIZE ( plb_M_MSize[0:1] ),
      .C405PLBDCUORDERED ( plb_M_ordered[0] ),
      .C405PLBDCUPRIORITY ( plb_M_priority[0:1] ),
      .C405PLBDCURDBURST ( plb_M_rdBurst[0] ),
      .C405PLBDCUREQUEST ( plb_M_request[0] ),
      .C405PLBDCUSIZE ( plb_M_size[0:3] ),
      .C405PLBDCUTYPE ( plb_M_type[0:2] ),
      .C405PLBDCUWRBURST ( plb_M_wrBurst[0] ),
      .C405PLBDCUWRDBUS ( plb_M_wrDBus[0:63] ),
      .C405PLBDCUCACHEABLE (  ),
      .C405PLBDCUWRITETHRU (  ),
      .PLBC405DCUADDRACK ( plb_PLB_MAddrAck[0] ),
      .PLBC405DCUBUSY ( plb_PLB_MBusy[0] ),
      .PLBC405DCUERR ( plb_PLB_MErr[0] ),
      .PLBC405DCURDBTERM ( plb_PLB_MRdBTerm[0] ),
      .PLBC405DCURDDACK ( plb_PLB_MRdDAck[0] ),
      .PLBC405DCURDDBUS ( plb_PLB_MRdDBus[0:63] ),
      .PLBC405DCURDWDADDR ( plb_PLB_MRdWdAddr[0:3] ),
      .PLBC405DCUREARBITRATE ( plb_PLB_MRearbitrate[0] ),
      .PLBC405DCUWRBTERM ( plb_PLB_MWrBTerm[0] ),
      .PLBC405DCUWRDACK ( plb_PLB_MWrDAck[0] ),
      .PLBC405DCUSSIZE ( plb_PLB_MSSize[0:1] ),
      .PLBC405DCUSERR ( plb_PLB_SMErr[0] ),
      .PLBC405DCUSBUSYS ( plb_PLB_SMBusy[0] ),
      .BRAMDSOCMCLK ( net_gnd0 ),
      .BRAMDSOCMRDDBUS ( net_gnd32 ),
      .DSARCVALUE ( net_gnd8 ),
      .DSCNTLVALUE ( net_gnd8 ),
      .DSOCMBRAMABUS (  ),
      .DSOCMBRAMBYTEWRITE (  ),
      .DSOCMBRAMEN (  ),
      .DSOCMBRAMWRDBUS (  ),
      .DSOCMBUSY (  ),
      .BRAMISOCMCLK ( net_gnd0 ),
      .BRAMISOCMRDDBUS ( net_gnd64 ),
      .ISARCVALUE ( net_gnd8 ),
      .ISCNTLVALUE ( net_gnd8 ),
      .ISOCMBRAMEN (  ),
      .ISOCMBRAMEVENWRITEEN (  ),
      .ISOCMBRAMODDWRITEEN (  ),
      .ISOCMBRAMRDABUS (  ),
      .ISOCMBRAMWRABUS (  ),
      .ISOCMBRAMWRDBUS (  ),
      .C405DCRABUS (  ),
      .C405DCRDBUSOUT (  ),
      .C405DCRREAD (  ),
      .C405DCRWRITE (  ),
      .DCRC405ACK ( net_gnd0 ),
      .DCRC405DBUSIN ( net_gnd32 ),
      .EICC405CRITINPUTIRQ ( net_gnd0 ),
      .EICC405EXTINPUTIRQ ( net_gnd0 ),
      .C405JTGCAPTUREDR (  ),
      .C405JTGEXTEST (  ),
      .C405JTGPGMOUT (  ),
      .C405JTGSHIFTDR (  ),
      .C405JTGTDO (  ),
      .C405JTGTDOEN (  ),
      .C405JTGUPDATEDR (  ),
      .MCBJTAGEN ( net_vcc0 ),
      .JTGC405BNDSCANTDO ( net_gnd0 ),
      .JTGC405TCK ( net_gnd0 ),
      .JTGC405TDI ( net_gnd0 ),
      .JTGC405TMS ( net_gnd0 ),
      .JTGC405TRSTNEG ( net_gnd0 ),
      .C405DBGMSRWE (  ),
      .C405DBGSTOPACK (  ),
      .C405DBGWBCOMPLETE (  ),
      .C405DBGWBFULL (  ),
      .C405DBGWBIAR (  ),
      .DBGC405DEBUGHALT ( net_gnd0 ),
      .DBGC405EXTBUSHOLDACK ( net_gnd0 ),
      .DBGC405UNCONDDEBUGEVENT ( net_gnd0 ),
      .C405TRCCYCLE (  ),
      .C405TRCEVENEXECUTIONSTATUS (  ),
      .C405TRCODDEXECUTIONSTATUS (  ),
      .C405TRCTRACESTATUS (  ),
      .C405TRCTRIGGEREVENTOUT (  ),
      .C405TRCTRIGGEREVENTTYPE (  ),
      .TRCC405TRACEDISABLE ( net_gnd0 ),
      .TRCC405TRIGGEREVENTIN ( net_gnd0 )
    );

  reset_block_wrapper
    reset_block (
      .Slowest_sync_clk ( sys_clk_s ),
      .Ext_Reset_In ( sys_rst_s ),
      .Aux_Reset_In ( net_gnd0 ),
      .Core_Reset_Req ( C405RSTCORERESETREQ ),
      .Chip_Reset_Req ( C405RSTCHIPRESETREQ ),
      .System_Reset_Req ( C405RSTSYSRESETREQ ),
      .Dcm_locked ( dcm_0_lock ),
      .Rstc405resetcore ( RSTC405RESETCORE ),
      .Rstc405resetchip ( RSTC405RESETCHIP ),
      .Rstc405resetsys ( RSTC405RESETSYS ),
      .Bus_Struct_Reset ( sys_bus_reset[0:0] ),
      .Peripheral_Reset (  )
    );

  plb_wrapper
    plb (
      .PLB_Clk ( sys_clk_s ),
      .SYS_Rst ( sys_bus_reset[0] ),
      .PLB_Rst ( plb_PLB_Rst ),
      .PLB_dcrAck (  ),
      .PLB_dcrDBus (  ),
      .DCR_ABus ( net_gnd10 ),
      .DCR_DBus ( net_gnd32 ),
      .DCR_Read ( net_gnd0 ),
      .DCR_Write ( net_gnd0 ),
      .M_ABus ( plb_M_ABus ),
      .M_BE ( plb_M_BE ),
      .M_RNW ( plb_M_RNW ),
      .M_abort ( plb_M_abort ),
      .M_busLock ( plb_M_busLock ),
      .M_compress ( plb_M_compress ),
      .M_guarded ( plb_M_guarded ),
      .M_lockErr ( plb_M_lockErr ),
      .M_MSize ( plb_M_MSize ),
      .M_ordered ( plb_M_ordered ),
      .M_priority ( plb_M_priority ),
      .M_rdBurst ( plb_M_rdBurst ),
      .M_request ( plb_M_request ),
      .M_size ( plb_M_size ),
      .M_type ( plb_M_type ),
      .M_wrBurst ( plb_M_wrBurst ),
      .M_wrDBus ( plb_M_wrDBus ),
      .Sl_addrAck ( plb_Sl_addrAck ),
      .Sl_MErr ( plb_Sl_MErr ),
      .Sl_MBusy ( plb_Sl_MBusy ),
      .Sl_rdBTerm ( plb_Sl_rdBTerm ),
      .Sl_rdComp ( plb_Sl_rdComp ),
      .Sl_rdDAck ( plb_Sl_rdDAck ),
      .Sl_rdDBus ( plb_Sl_rdDBus ),
      .Sl_rdWdAddr ( plb_Sl_rdWdAddr ),
      .Sl_rearbitrate ( plb_Sl_rearbitrate ),
      .Sl_SSize ( plb_Sl_SSize ),
      .Sl_wait ( plb_Sl_wait ),
      .Sl_wrBTerm ( plb_Sl_wrBTerm ),
      .Sl_wrComp ( plb_Sl_wrComp ),
      .Sl_wrDAck ( plb_Sl_wrDAck ),
      .PLB_ABus ( plb_PLB_ABus ),
      .PLB_BE ( plb_PLB_BE ),
      .PLB_MAddrAck ( plb_PLB_MAddrAck ),
      .PLB_MBusy ( plb_PLB_MBusy ),
      .PLB_MErr ( plb_PLB_MErr ),
      .PLB_MRdBTerm ( plb_PLB_MRdBTerm ),
      .PLB_MRdDAck ( plb_PLB_MRdDAck ),
      .PLB_MRdDBus ( plb_PLB_MRdDBus ),
      .PLB_MRdWdAddr ( plb_PLB_MRdWdAddr ),
      .PLB_MRearbitrate ( plb_PLB_MRearbitrate ),
      .PLB_MWrBTerm ( plb_PLB_MWrBTerm ),
      .PLB_MWrDAck ( plb_PLB_MWrDAck ),