`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    02:13:37 05/26/07
// Design Name:    
// Module Name:    pipadd
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pipadd(clk,indata,addout,shifts);
input[31:0] indata;
input clk;
output shifts;
output[31:0] addout;
reg shifts;
reg[31:0] addout="0000000000000000";
always@(posedge clk)
begin
shifts<=1'b1;
addout<=indata+32'h00000077;
end

endmodule