#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Actel\Libero8.0\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: MICROSOF-30888C

#Implementation: synthesis

#Fri Feb 22 19:01:36 2008

$ Start of Compile
#Fri Feb 22 19:01:36 2008

Synplicity Verilog Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v"
@I::"F:\Actel_prj\myprj\simple_beep\smartgen\PLL_25M\PLL_25M.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\key_measure.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_note_A_440HZ.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_440HZ.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_parameter.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_ambulance_siren.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\divide_by12.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_tune.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_police_siren.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v"
@I::"F:\Actel_prj\myprj\simple_beep\hdl\main.v"
Verilog syntax check successful!
File F:\Actel_prj\myprj\simple_beep\hdl\divide_by12.v changed - recompiling
File F:\Actel_prj\myprj\simple_beep\hdl\music_tune.v changed - recompiling
File F:\Actel_prj\myprj\simple_beep\hdl\music_police_siren.v changed - recompiling
File F:\Actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v changed - recompiling
File F:\Actel_prj\myprj\simple_beep\hdl\main.v changed - recompiling
Selecting top level module main
@N: CG364 :"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\smartgen\PLL_25M\PLL_25M.v":5:7:5:13|Synthesizing module PLL_25M

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\key_measure.v":4:7:4:17|Synthesizing module key_measure

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v":18:7:18:23|Synthesizing module music_simple_beep

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_note_A_440HZ.v":9:7:9:24|Synthesizing module music_note_A_440HZ

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_440HZ.v":10:7:10:17|Synthesizing module music_440HZ

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_parameter.v":7:7:7:21|Synthesizing module music_parameter

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_ambulance_siren.v":10:7:10:27|Synthesizing module music_ambulance_siren

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\divide_by12.v":14:7:14:17|Synthesizing module divide_by12

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_tune.v":3:7:3:16|Synthesizing module music_tune

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_police_siren.v":3:7:3:24|Synthesizing module music_police_siren

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v":9:7:9:30|Synthesizing module music_high_speed_pursuit

@N: CG364 :"F:\Actel_prj\myprj\simple_beep\hdl\main.v":8:7:8:10|Synthesizing module main

@W: CS148 :"F:\Actel_prj\myprj\simple_beep\hdl\main.v":28:11:28:20|Undriven input OADIVRST, tying to 0
@W: CL189 :"F:\Actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v":21:0:21:5|Register bit counter[14] is always 0, optimizing ...
@W: CL171 :"F:\Actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v":21:0:21:5|Pruning Register bit <14> of counter[14:0] 

@W: CL171 :"F:\Actel_prj\myprj\simple_beep\hdl\music_police_siren.v":22:0:22:5|Pruning Register bit <14> of counter[14:0] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 22 19:01:39 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 8.8.0, Build 015R, Built Apr 15 2007 16:31:14
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8A1
@N: MF249 |Running in 32-bit mode.
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


Automatic dissolve at startup in view:work.main(verilog) of PLL_25M_U0(PLL_25M)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 42MB)
@N: MF238 :"f:\actel_prj\myprj\simple_beep\hdl\key_measure.v":47:22:47:34|Found 4 bit incrementor, 'un6_key_temp[3:0]'
@N: MF238 :"f:\actel_prj\myprj\simple_beep\hdl\key_measure.v":26:9:26:16|Found 17 bit incrementor, 'un4_cnt[16:0]'
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_simple_beep.v":24:0:24:5|Found counter in view:work.music_simple_beep(verilog) inst counter[15:0]
@N: MF238 :"f:\actel_prj\myprj\simple_beep\hdl\music_note_a_440hz.v":17:71:17:80|Found 16 bit incrementor, 'un4_counter[15:0]'
@N: MF238 :"f:\actel_prj\myprj\simple_beep\hdl\music_440hz.v":18:71:18:80|Found 15 bit incrementor, 'un4_counter_1[14:0]'
@N: MF239 :"f:\actel_prj\myprj\simple_beep\hdl\music_parameter.v":13:78:13:87|Found 15 bit decrementor, 'un4_counter[14:0]'
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_ambulance_siren.v":16:0:16:5|Found counter in view:work.music_ambulance_siren(verilog) inst tone[23:0]
@N: MF239 :"f:\actel_prj\myprj\simple_beep\hdl\music_ambulance_siren.v":23:17:23:26|Found 15 bit decrementor, 'un9_counter[14:0]'
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_tune.v":55:0:55:5|Found counter in view:work.music_tune(verilog) inst counter_note[8:0]
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_tune.v":12:0:12:5|Found counter in view:work.music_tune(verilog) inst tone[27:0]
@N: MO106 :"f:\actel_prj\myprj\simple_beep\hdl\music_tune.v":35:0:35:3|Found ROM, 'clkdivider[8:0]', 16 words by 9 bits 
@N: MF239 :"f:\actel_prj\myprj\simple_beep\hdl\music_tune.v":67:20:67:36|Found 8 bit decrementor, 'un74_counter_octave[7:0]'
@N: MO106 :"f:\actel_prj\myprj\simple_beep\hdl\divide_by12.v":25:0:25:3|Found ROM, 'quotient_1[2:0]', 16 words by 3 bits 
@N: MO106 :"f:\actel_prj\myprj\simple_beep\hdl\divide_by12.v":25:0:25:3|Found ROM, 'remain_bit3_bit2[1:0]', 16 words by 2 bits 
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_police_siren.v":8:0:8:5|Found counter in view:work.music_police_siren(verilog) inst tone[22:0]
@N: MF239 :"f:\actel_prj\myprj\simple_beep\hdl\music_police_siren.v":22:76:22:85|Found 14 bit decrementor, 'un1_counter[13:0]'
@N:"f:\actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v":14:0:14:5|Found counter in view:work.music_high_speed_pursuit(verilog) inst tone[27:0]
@N: MF239 :"f:\actel_prj\myprj\simple_beep\hdl\music_high_speed_pursuit.v":21:76:21:85|Found 14 bit decrementor, 'un1_counter[13:0]'

Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 42MB peak: 43MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:04s; Memory used current: 42MB peak: 44MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 43MB peak: 44MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 43MB peak: 44MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 42MB peak: 44MB)

Finished preparing to map (Time elapsed 0h:00m:05s; Memory used current: 45MB peak: 45MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes                
------------------------------------------------------------
rst_K2_pad / Y                 21 : 4 asynchronous set/reset
U7.counter11 / Y               14                           
U6.counter11 / Y               14                           
U5.counter_note11 / Y          24                           
============================================================

Replicating Combinational Instance U5.counter_note11, fanout 24 segments 2
Replicating Combinational Instance U6.counter11, fanout 14 segments 2
Replicating Combinational Instance U7.counter11, fanout 14 segments 2
Buffering rst_K2_c, fanout 21 segments 2

Finished technology mapping (Time elapsed 0h:00m:05s; Memory used current: 44MB peak: 46MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 44MB peak: 46MB)

Added 1 Buffers
Added 3 Cells via replication
	Added 0 Sequential Cells via replication
	Added 3 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 44MB peak: 46MB)
Writing Analyst data base F:\Actel_prj\myprj\simple_beep\synthesis\main.srm
@N: BN225 |Writing default property annotation file F:\Actel_prj\myprj\simple_beep\synthesis\main.map.
Writing EDIF Netlist and constraint files
Found clock main|PLL_25M_U0.clk_25m_inferred_clock with period 10.00ns 
Found clock key_measure|key_done_inferred_clock with period 10.00ns 
Found clock key_measure|cnt_inferred_clock[16] with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Feb 22 19:01:51 2008
#


Top view:               main
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary