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?? main.edn

?? 基于FPGA的VHDL編程實現(xiàn)各種音頻信號
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(edif main
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2008 2 22 19 1 50)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "8.8.0, Build 015R"))
     )
   )
  (library fusion
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell PLLINT (cellType GENERIC)
      (property dont_use (integer 1))
      (property dont_touch (string "true"))
      (property area (integer 0))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property max_fanout (integer 2000))
           (property function (string "A"))
 )
           (port A (direction INPUT)
           (property capacitance (integer 1))
 )
         )
        (property area (integer 0))
       )
    )
    (cell PLL (cellType GENERIC)
      (property dont_touch (string "true"))
      (property dont_use (integer 1))
      (property area (integer 0))
       (view prim (viewType NETLIST)
         (interface
           (port GLA (direction OUTPUT)
 )
           (port GLB (direction OUTPUT)
 )
           (port GLC (direction OUTPUT)
 )
           (port LOCK (direction OUTPUT)
 )
           (port YB (direction OUTPUT)
 )
           (port YC (direction OUTPUT)
 )
           (port CLKA (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLA0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLA1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLA2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLA3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLA4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLB0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLB1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLB2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLB3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLB4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLC0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLC1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLC2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLC3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYGLC4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYB0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYB1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYB2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYB3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYB4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYC0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYC1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYC2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYC3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port DLYYC4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port EXTFB (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV5 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDIV6 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDLY0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDLY1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDLY2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDLY3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBDLY4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBSEL0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FBSEL1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV5 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port FINDIV6 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIV0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIV1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIV2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIV3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIV4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIVHALF (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OADIVRST (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OAMUX0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OAMUX1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OAMUX2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBDIV0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBDIV1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBDIV2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBDIV3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBDIV4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBMUX0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBMUX1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OBMUX2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCDIV0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCDIV1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCDIV2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCDIV3 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCDIV4 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCMUX0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCMUX1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port OCMUX2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port POWERDOWN (direction INPUT)
           (property capacitance (integer 1))
 )
           (port VCOSEL0 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port VCOSEL1 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port VCOSEL2 (direction INPUT)
           (property capacitance (integer 1))
 )
           (port XDLYSEL (direction INPUT)
           (property capacitance (integer 1))
 )
         )
        (property area (integer 0))
       )
    )
    (cell XOR2 (cellType GENERIC)
      (property dont_touch (string "false"))
      (property area (integer 1))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property max_fanout (integer 2000))
           (property function (string "A ^ B"))
 )
           (port A (direction INPUT)
           (property capacitance (integer 1))
 )
           (port B (direction INPUT)
           (property capacitance (integer 1))
 )
         )
        (property is_combinational (integer 1))
        (property area (integer 1))
       )
    )
    (cell XNOR2 (cellType GENERIC)
      (property dont_touch (string "false"))
      (property area (integer 1))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property max_fanout (integer 2000))
           (property function (string "!(A ^ B)"))
 )
           (port A (direction INPUT)
           (property capacitance (integer 1))
 )
           (port B (direction INPUT)
           (property capacitance (integer 1))
 )
         )
        (property is_combinational (integer 1))
        (property area (integer 1))
       )
    )
    (cell VCC (cellType GENERIC)
      (property dont_touch (string "false"))
      (property area (integer 0))
       (view prim (viewType NETLIST)
         (interface

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