@E
@ 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Feb 22 12:56:01 2008
#
#
#OPTIONS:"|-fixsmult|-autosm|-I|F:\\Actel_prj\\myprj\\simple_beep\\synthesis\\|-I|C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib|-v95|-devicelib|C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib\\proasic\\fusion.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-ram|-ll|2000"
#CUR:"C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\bin\\c_ver.exe":1176452670
#CUR:"C:\\Actel\\Libero8.0\\Synplify\\Synplify_88A1\\lib\\proasic\\fusion.v":1149579214
#CUR:"F:\\Actel_prj\\myprj\\simple_beep\\hdl\\music_simple_beep.v":1203656134
f "C:\Actel\Libero8.0\Synplify\Synplify_88A1\lib\proasic\fusion.v"; # file 0
af .is_verilog 1;
f "F:\Actel_prj\myprj\simple_beep\hdl\music_simple_beep.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@44:U::(4.U:dFRIsl	RkO#H_l#Hb_DCLbCCRsPCHoDF;P
NR#3HPHCsDRFo4N;
PHR3#C_PsFHDo;R4
RNP3HFsolhNClR"kO#H_l#Hb_DCLbCC"
;

@HR@44:g::n4Ug:R	ODR	OD;H
NR03sDs_FHNoMl"CRO"D	;



@FR@.4:j::(.4j:dbR#CCN	sFROkCM0s6r49N;
HsR30FD_sMHoNRlC"C#bNs	C"b;
Rj@@:44::.4:Rk0sCsR0k0CRs;kC
@bR@4j::44::V.RNCD#RDVN#VCRNCD#;R
b@:@4.dc:dc:.:Rc.NR88OMFk0_Cs46r4:Rj9OMFk0_Cs46r4:Rj9OMFk0rCs4j6:9sR0k
C;b@R@4c:.:.j:cR:68RVVOMFk0rCs4j6:9FROkCM0s6r4:Rj9OMFk0_Cs46r4:Rj9O;D	
RNH3Ds0_HFsolMNCOR"F0kMC;s"

C;