// divide_by12.v
/*********************************************************************************************
The "divide by 12" module takes a 6 bits value (numerator) and divides it by 12 (denominator).
 That gives us a 3 bits quotient (0..5) and a 4 bits remainder (0..11). We tried to use the FPGA 
 vendor provided "divide" function, but it is optimized for general divide, while here the 
 denominator is fixed. So a specific divide function was made.

To divide by 12, the trick is to divide by 4 first, then by 3.
Dividing by 4 is trivial: we remove 2 bits out of the numerator, and copy it to the remainder.
 So we are left with 6-2=4 bits to divide by the value "3". That's easily done with a lookup table.

*********************************************************************************************/

module divide_by12(numer, quotient, remain);
input [5:0] numer;
output [2:0] quotient;
output [3:0] remain;

reg [2:0] quotient;
reg [3:0] remain_bit3_bit2;

assign remain = {remain_bit3_bit2, numer[1:0]}; // the first 2 bits are copied through

always @(numer[5:2])                            // and just do a divide by "3" on the remaining bits
case(numer[5:2])
  0: begin quotient = 0; remain_bit3_bit2 = 0; end
  1: begin quotient = 0; remain_bit3_bit2 = 1; end
  2: begin quotient = 0; remain_bit3_bit2 = 2; end
  3: begin quotient = 1; remain_bit3_bit2 = 0; end
  4: begin quotient = 1; remain_bit3_bit2 = 1; end
  5: begin quotient = 1; remain_bit3_bit2 = 2; end
  6: begin quotient = 2; remain_bit3_bit2 = 0; end
  7: begin quotient = 2; remain_bit3_bit2 = 1; end
  8: begin quotient = 2; remain_bit3_bit2 = 2; end
  9: begin quotient = 3; remain_bit3_bit2 = 0; end
 10: begin quotient = 3; remain_bit3_bit2 = 1; end
 11: begin quotient = 3; remain_bit3_bit2 = 2; end
 12: begin quotient = 4; remain_bit3_bit2 = 0; end
 13: begin quotient = 4; remain_bit3_bit2 = 1; end
 14: begin quotient = 4; remain_bit3_bit2 = 2; end
 15: begin quotient = 5; remain_bit3_bit2 = 0; end
endcase

endmodule