?? adder8bit.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8bit is
port(cin:in std_logic;
a,b:in std_logic_vector(7 downto 0);
s:out std_logic_vector(7 downto 0);
cout:out std_logic);
end adder8bit;
architecture beh2 of adder8bit is
component adder4bit
port(cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
signal carry_out:std_logic;
begin
u1:adder4bit port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out);
u2:adder4bit port map(cin=>carry_out,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>cout);
end beh2;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -