-- and2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity and2 is
  port(a,b:in std_logic;
         y:out std_logic);
end and2;
architecture behav of and2 is
signal yo:std_logic:='1'; --the initial value
  begin
   y<=yo; 
   yo<=a and b;
  end behav;