?? tf.vhd
字號:
--tf
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity tf is
port(clk:in std_logic;
q,nq:out std_logic);
end entity tf;
architecture rtl of tf is
signal qn:std_logic:='0';--the initial value
begin
q<=qn;
nq<=not qn;
process(clk)
begin
if(clk'event and clk='0') then
qn<=not qn;
end if;
end process;
end rtl;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -