package width is
constant N1:integer:=2;
constant N2:integer:=16;
end width;
USE work.width.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test3 is
port(clk:in std_logic;
	rxd:in std_logic;
	txd:out std_logic);
end test3;
architecture behav of test3 is
signal clk1,clk2,ri,cs,wr,ti:std_logic;
signal q1,q2:std_logic_vector(7 downto 0);
component fredivn
GENERIC (N:positive);
port(clkin:in std_logic;
	clkout :out std_logic);
end component;
component D_flipflop 
port(ri,clk:in std_logic;
	datain :in std_logic_vector(7 downto 0);
	dataout :out std_logic_vector(7 downto 0);
	wr:out std_logic);
end component;
component rxd3 
port(clk,rx:in std_logic;
	sig1:buffer std_logic;
		q:out std_logic_vector(7 downto 0));
end component;
component txd5 
port
	(indata:in std_logic_vector(7 downto 0);
	 cs,wr,clk:in std_logic;
	 txd,ti:out std_logic);
end component;
begin
u1:fredivn
	generic map(N=>N1)
	port map(clk,clk1);
u2:fredivn
	generic map(N=>N2)
	port map(clk1,clk2);
u3:D_flipflop
	port map(ri,clk2,q1,q2,wr);
u4:rxd3
	port map(clk1,rxd,ri,q1);
u5:txd5
	port map(q2,cs,wr,clk2,txd,ti);
cs<='0';
end behav;