?? jioujiaoyan1.vhd
字號(hào):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan1 is
port(a:in std_logic_vector(7 downto 0);
q:out std_logic);
end jioujiaoyan1;
architecture rtl of jioujiaoyan1 is
begin
PROCESS(a)
variable tmp:std_logic;
BEGIN
tmp:='0';
i:='0';
while (i < a'high ) loop
tmp:=tmp xor a(i);
i:=i+1;
end loop;
q<=tmp;
END PROCESS;
end rtl;
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