?? mux4to1.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux4to1 is
port(a,b,c,d:in std_logic;
sel:in std_logic_vector(1 downto 0);
q:out std_logic);
end mux4to1;
architecture rtl of mux4to1 is
begin
PROCESS(sel, a, b, c, d)
BEGIN
CASE sel IS
WHEN "00" =>
q <= a;
WHEN "01" =>
q <= b;
WHEN "10" =>
q <= c;
WHEN OTHERS =>
q <= d;
END CASE;
END PROCESS;
end rtl;
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