library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity myand is
GENERIC (sreg_width:integer:=8);
port(indata:in std_logic_vector(sreg_width-1 downto 0);
	q :out std_logic);
end myand;
architecture rtl of myand is
signal z:std_logic_vector(sreg_width downto 0);
component myand1
port(a,b:in std_logic;
	q :out std_logic);
end component;
begin
z(sreg_width)<='1';
g1:for i in sreg_width-1 downto 0 generate
	u1:myand1 port map(z(i+1),indata(i),z(i));
end generate;
q<=z(0);
end rtl;