library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux3to1_1 is
	port(a,c :in std_logic;
			b :in std_logic;
			sel1,sel2:in std_logic;
			q:out std_logic);
end mux3to1_1;
architecture rtl of mux3to1_1 is
signal d:std_logic;
COMPONENT mux2to1
		port(a :in std_logic;
			b :in std_logic;
			sel:in std_logic;
			c:out std_logic);
END COMPONENT;
begin
u1: mux2to1  PORT MAP (a,b,sel1,d);
u2: mux2to1  PORT MAP (c,d,sel2,q);
end rtl;