;++
;Module name:
;
;        INIT.s
;
;Abstract:
;
;        EP7312 processor Start up assembly code file.
;
;Author:
;
;        Michael Anburaj
;        URL              : http:\\embedded.n3.net      Email : embeddedeng@hotmail.com
;
;Environment:
;
;        Processor        : EP73XX (32 bit ARM720T RISC core from CIRRUS)
;        IDE              : SDT 2.51 & ADS 1.0
;
;--

; The following are condtional assembly flags.  Leave commented if you don't want
; to assemble the corresponding code block.
                                
;MMU_enabled  EQU 0x1               ;these can be defined in the project file
DRAM_enabled  EQU 0x1               ;if commented, then not defined by default
;FIQ_enabled  EQU 0x1               ;

        IF :DEF: MMU_enabled
IBADDR        EQU 0x00020000              ;plus 0x20 is the RW base address -linker setting
        ELSE
IBADDR        EQU 0x60000000              ;plus 0x20 is the RW base address -linker setting
        ENDIF

SBADDR        EQU 0x80000000              ;This base address should be used before MMU mapping

_SVC_STKSIZE  EQU 1024*1
_UND_STKSIZE  EQU 256
_ABT_STKSIZE  EQU 256
_IRQ_STKSIZE  EQU 1024*1
_FIQ_STKSIZE  EQU 256


;Interrupt Control
rMEMCFG1      EQU SBADDR+0x0180
rMEMCFG2      EQU SBADDR+0x01C0
rINTMR1       EQU SBADDR+0x0280
rINTMR2       EQU SBADDR+0x1280
rINTSR1       EQU SBADDR+0x0240
rINTSR2       EQU SBADDR+0x1240
rSDCONF       EQU SBADDR+0x2300
rSDRFPR       EQU SBADDR+0x2340
rSYSCON2      EQU SBADDR+0x1100
rSYSCON3      EQU SBADDR+0x2200

;Pre-defined constants
USERMODE      EQU 0x10
FIQMODE       EQU 0x11
IRQMODE       EQU 0x12
SVCMODE       EQU 0x13
ABORTMODE     EQU 0x17
UNDEFMODE     EQU 0x1b
MODEMASK      EQU 0x1f
NOINT         EQU 0xc0


        MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
        ;sub sp,sp,#4
        ;stmfd sp!,{r0}
        ;ldr r0,=$HandleLabel
        ;ldr r0,[r0]
        ;str r0,[sp,#4]
        ;ldmfd sp!,{r0,pc}
        ldr pc,=$HandleLabel
        MEND


        AREA  |Assembly$$code|, CODE, READONLY

        ENTRY

        b ResetHandler              ;for debug
        b .              ;handlerUndef
        b .                ;SWI interrupt handler
        b .             ;handlerPAbort
        b .             ;handlerDAbort
        b .                         ;handlerReserved
         
        b .                ;handlerIRQ
 
        b .                ;handlerFIQ

;        IMPORT UCOS_IRQHandler   
;        IMPORT __HaltUndef
;        IMPORT __HaltSwi
;        IMPORT __HaltPabort
;        IMPORT __HaltDabort
;        IMPORT __HaltFiq
     
;HandlerFIQ     HANDLER __HaltFiq
;HandlerIRQ     HANDLER UCOS_IRQHandler
;HandlerUndef   HANDLER __HaltUndef
;HandlerSWI     HANDLER __HaltSwi
;HandlerDabort  HANDLER __HaltDabort
;HandlerPabort  HANDLER __HaltPabort
        
;HandlerFIQ     HANDLER HandleFIQ
;HandlerIRQ     HANDLER HandleIRQ
;HandlerUndef   HANDLER HandleUndef
;HandlerSWI     HANDLER HandleSWI
;HandlerDabort  HANDLER HandleDabort
;HandlerPabort  HANDLER HandlePabort


;*****************************************************************************
;
; ResetHandler is the startup code to be used
;
;*****************************************************************************
ResetHandler
        ;
        ; Setup the MMU for 32 bit code and data.
        ;
        ldr r0,=0x00000070
        mcr p15,0,r0,c1,c0,0

        ldr r0,=0x00000000
        ;        
        ;disable all interrupts (they should be disabled on reset, but just in case...)

        ldr r12,=rINTMR1
        str r0,[r12]                ;INTMR1 = 0x8000.0280
        ldr r12,=rINTMR2
        str r0,[r12]                ;INTMR2 = 0x8000.1280
;
;***************************************************************************************
; Do this section only if DRAM is required.
        IF (:DEF: DRAM_enabled)
        
DRAMControlvalue  EQU 0x00000522    ; CASLAT=3, SDSIZE=256Mb, SDWIDTH=32, CLKCTL=0, SDACTIVE=1
DRAMConfigvalue   EQU 0x00000100    ; REFRATE=7.11uS at 36MHz BCLK

        ; Enable SDRAM Bank 0 and Bank 1 for EP73xx
        ;
        ldr r1,=DRAMControlvalue
        ldr r12,=rSDCONF
        str r1,[r12]                ; store in SDCONF

        ldr r1,=DRAMConfigvalue
        ldr r12,=rSDRFPR
        str r1,[r12]                ; store value in SDRFPR

        ;
        ;        Stub for memory test
        ;
        ;
        ; Set SYSCON2 to zero (default value, step not necessary).  Bit 2 sets x32 DRAM
        ;
        ldr r12,=rSYSCON2
        str r0,[r12]                ;init syscon2 register at 0x8000.1100
;**********************************************************************************************
; End of DRAM intialization
                ENDIF
         
        ;
        ; Set bits 1:2 in SYSCON3 for 18M MHz clock speed (default is 18MHz on reset)
        ;
        ldr r1,=0x00
        ldr r12,=rSYSCON3
        str r1,[r12]                ;init syscon3 register at 0x8000.2200

; Now configure the MemConfig register to get the following:
;
; nCS0 = NOR FLASH, 16-bit, 3 wait states
; nCS1 = NAND FLASH, 32-bit, 2 wait states
; nCS2 = Ethernet, 16-bit, 8 wait states (was 32-bit =0x00)
; nCS3 = Parallel/Keyboard/GPIOs, 32-bit, 1 wait state
; nCS4 = USB, 8-bit, 1 wait state, 2 w/s random (was 32-bit, =0x3c)
; nCS5 = Unused/general purpose, 32-bit, 8 wait states
;
                
MemConfig1value  EQU 0x00050004
MemConfig2value  EQU 0x00000000     ;boot rom and internal SRAM are ignored 
        
        ;
        ; configure nCS0-nCS3
        ;
        ldr r1,=MemConfig1value
        ldr r12,=rMEMCFG1
        str r1,[r12]                ;MEMCFG1 = 0x8000.0180
        ;
        ; configure nCS4 &nCS5
        ;
        ldr r1,=MemConfig2value
        ldr r12,=rMEMCFG2
        str r1,[r12]                ;MEMCFG2 = 0x8000.01c0

; **************************************************************************
; Define Stacks
; The follow section defines the stack pointer for IRQ and SVC modes.
; This is optional as the debugger will assign it's own stack area with the
; $top_of_memory variable in "debugger internals".
; However, this code is necessary if this program is used to launch an 
; embedded applications in C or assembly.
; **************************************************************************
        ldr sp,=SVCStack            ;Why?

        bl InitStacks

;********************************************************************
; End of Stack Setup
;********************************************************************
        ;
        ;
;********************************************************************
;
; Set up the MMU.  Start by flushing the cache and TLB.
; This section may be eliminated if MMU is not desired.
;********************************************************************
        ;
        IF (:DEF: MMU_enabled)
        ldr r0,=0x00000000
        mcr p15,0,r0,c5,c0
        mcr p15,0,r0,c7,c0

        ;
        ; Set user mode access for all 16 domains.
        ;
        ldr r0,=0x55555555
        mcr p15,0,r0,c3,c0

        ;
        ; Tell the MMU where to find the page table.
        ;
        IMPORT  PageTable
        ldr r0,=PageTable
        mcr p15,0,r0,c2,c0

        ;
        ; Enable the MMU.
        ;
        ldr r0,=0x0000007d
        mcr p15,0,r0,c1,c0
        ;
        ;
        ; There should always be two NOP instructions following the enable or
        ; disable of the MMU.
        ;
        mov r0,r0
        mov r0,r0
;*****************************************************************************
; End of MMU intialization
;*****************************************************************************
        ENDIF                       ;end conditional assembly

        ;
        ; Copy the read-write data block from ROM to RAM.
        ;

        IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
        IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
        IMPORT  |Image$$ZI$$Base|   ; Base and limit of area
        IMPORT  |Image$$ZI$$Limit|  ; to zero initialise

        LDR r0,=|Image$$RO$$Limit|  ; Get pointer to ROM data
        LDR r1,=|Image$$RW$$Base|   ; and RAM copy
        LDR r3,=|Image$$ZI$$Base|        
        ;Zero init base => top of initialised data
                        
        CMP r0,r1                   ; Check that they are different
        BEQ %F1
0                
        CMP r1,r3                   ; Copy init data
        LDRCC r2,[r0],#4
        STRCC r2,[r1],#4
        BCC %B0
1                
        LDR r1,=|Image$$ZI$$Limit|  ; Top of zero init segment
        MOV r2,#0
2                
        CMP r3,r1                   ; Zero init
        STRCC r2,[r3],#4
        BCC %B2



program
        ;
        ; Call the actual C program program.
        ;

	;///////////////////////
	;set uart by zx 07.22.2002

	;mov	r1, #0x100	;	/* UART enable bit in SYSCON[1|2] */
	;str	r1, [r0, #0x100]	;/* enable UART1 in SYSCON1 */
	;add	r2, r0, #0x1100	;	/* load address of SYSCON2 in r2 */
	;str	r1, [r2]		;/* enable UART2 in SYSCON2 */

	;mov	r1, #0x00060000	;	/* UART 8-bit data length */
	;orr	r1, r1, #23	;	/* UART 9600 bps */
	;str	r1, [r0, #0x4C0]	;/* set UART1 bit rate/line control */
	;add	r2, r0, #0x14C0	;	/* load address of UBRLCR2 in r2 */
	;str	r1, [r2]		;/* set UART2 bit rate/line control */
	;////////////////////////////








        IMPORT C_vMain
        bl C_vMain                  ;C Entry
;
; Normally, the program should not return, but just in case, branch to the 
; reset vector and start over.

        b ResetHandler              ; Precautionary


InitStacks
        ;Don't use DRAM,such as stmfd,ldmfd......
        ;SVCstack is initialized before
        ;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
        
        mrs r0,cpsr
        bic r0,r0,#MODEMASK
        orr r1,r0,#UNDEFMODE|NOINT
        msr cpsr,r1
        ;msr cpsr_cxsf,r1            ;UndefMode
        ldr sp,=UndefStack
        
        orr r1,r0,#ABORTMODE|NOINT
        msr cpsr,r1       
        ;msr cpsr_cxsf,r1            ;AbortMode
        ldr sp,=AbortStack

        orr r1,r0,#IRQMODE|NOINT
        msr cpsr,r1
        ;msr cpsr_cxsf,r1            ;IRQMode
        ldr sp,=IRQStack
        
        orr r1,r0,#FIQMODE|NOINT
        msr cpsr,r1
        ;msr cpsr_cxsf,r1            ;FIQMode
        ldr sp,=FIQStack

        bic r0,r0,#MODEMASK|NOINT
        orr r1,r0,#SVCMODE
        msr cpsr,r1
        ;msr cpsr_cxsf,r1            ;SVCMode
        ldr sp,=SVCStack

        ;USER mode is not initialized.

        mov pc,lr                   ;The LR register may be not valid for the mode changes.

;
;*****************************************************************************
;
; Zero-initialized read/write data area for stacks.
; This area is determined by the RW value in the Linker under "entry and base".  
;*****************************************************************************
        AREA  SYS_STK, DATA, READWRITE, NOINIT

;*****************************************************************************
;
; Memory buffers to contain the stacks for the various processor modes which
; we will be using.
;
;*****************************************************************************

SVCStack_start    % _SVC_STKSIZE    ;0x2001800
SVCStack
UndefStack_start  % _UND_STKSIZE    ;0x2001C00
UndefStack
AbortStack_start  % _ABT_STKSIZE    ;0x2001D00
AbortStack
IRQStack_start    % _IRQ_STKSIZE    ;0x2001E00
IRQStack
FIQStack_start    % _FIQ_STKSIZE    ;0x2001F00
FIQStack                            ;0x2002000

        AREA  ISR_HOOK, DATA, READWRITE, NOINIT

        ^  IBADDR
HandleReset     # 4
HandleUndef     # 4
HandleSWI       # 4
HandlePabort    # 4
HandleDabort    # 4
HandleReserved  # 4
HandleIRQ       # 4
HandleFIQ       # 4

;
;*****************************************************************************
;        
        END