; N/A   ; None         ; 8.071 ns   ; Sev_Seg_Led_Data_n[3]~reg0 ; Sev_Seg_Led_Data_n[0] ; Clk        ;
; N/A   ; None         ; 8.068 ns   ; Sev_Seg_Led_Data_n[5]~reg0 ; Sev_Seg_Led_Data_n[5] ; Clk        ;
; N/A   ; None         ; 8.062 ns   ; Sev_Seg_Led_Sel_n[1]~reg0  ; Sev_Seg_Led_Sel_n[1]  ; Clk        ;
; N/A   ; None         ; 8.061 ns   ; Sev_Seg_Led_Data_n[4]~reg0 ; Sev_Seg_Led_Data_n[4] ; Clk        ;
; N/A   ; None         ; 7.747 ns   ; Sev_Seg_Led_Sel_n[3]~reg0  ; Sev_Seg_Led_Sel_n[3]  ; Clk        ;
; N/A   ; None         ; 7.739 ns   ; Sev_Seg_Led_Sel_n[2]~reg0  ; Sev_Seg_Led_Sel_n[2]  ; Clk        ;
; N/A   ; None         ; 7.696 ns   ; Sev_Seg_Led_Data_n[2]~reg0 ; Sev_Seg_Led_Data_n[2] ; Clk        ;
; N/A   ; None         ; 7.369 ns   ; Sev_Seg_Led_Data_n[3]~reg0 ; Sev_Seg_Led_Data_n[3] ; Clk        ;
+-------+--------------+------------+----------------------------+-----------------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Jul 02 22:08:20 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Segment2 -c Segment2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 295.07 MHz between source register "Cout[1]" and destination register "Cout[14]" (period= 3.389 ns)
    Info: + Longest register to register delay is 3.125 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y18_N5; Fanout = 2; REG Node = 'Cout[1]'
        Info: 2: + IC(0.754 ns) + CELL(0.621 ns) = 1.375 ns; Loc. = LCCOMB_X9_Y18_N4; Fanout = 2; COMB Node = 'Cout[1]~176'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.461 ns; Loc. = LCCOMB_X9_Y18_N6; Fanout = 2; COMB Node = 'Cout[2]~178'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.547 ns; Loc. = LCCOMB_X9_Y18_N8; Fanout = 2; COMB Node = 'Cout[3]~180'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.633 ns; Loc. = LCCOMB_X9_Y18_N10; Fanout = 2; COMB Node = 'Cout[4]~182'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.719 ns; Loc. = LCCOMB_X9_Y18_N12; Fanout = 2; COMB Node = 'Cout[5]~184'
        Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.909 ns; Loc. = LCCOMB_X9_Y18_N14; Fanout = 2; COMB Node = 'Cout[6]~186'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.995 ns; Loc. = LCCOMB_X9_Y18_N16; Fanout = 2; COMB Node = 'Cout[7]~188'
        Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.081 ns; Loc. = LCCOMB_X9_Y18_N18; Fanout = 2; COMB Node = 'Cout[8]~190'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.167 ns; Loc. = LCCOMB_X9_Y18_N20; Fanout = 2; COMB Node = 'Cout[9]~192'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.253 ns; Loc. = LCCOMB_X9_Y18_N22; Fanout = 2; COMB Node = 'Cout[10]~194'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.339 ns; Loc. = LCCOMB_X9_Y18_N24; Fanout = 2; COMB Node = 'Cout[11]~196'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.425 ns; Loc. = LCCOMB_X9_Y18_N26; Fanout = 2; COMB Node = 'Cout[12]~198'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.511 ns; Loc. = LCCOMB_X9_Y18_N28; Fanout = 1; COMB Node = 'Cout[13]~200'
        Info: 15: + IC(0.000 ns) + CELL(0.506 ns) = 3.017 ns; Loc. = LCCOMB_X9_Y18_N30; Fanout = 1; COMB Node = 'Cout[14]~201'
        Info: 16: + IC(0.000 ns) + CELL(0.108 ns) = 3.125 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 5; REG Node = 'Cout[14]'
        Info: Total cell delay = 2.371 ns ( 75.87 % )
        Info: Total interconnect delay = 0.754 ns ( 24.13 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 2.872 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X9_Y18_N31; Fanout = 5; REG Node = 'Cout[14]'
            Info: Total cell delay = 1.806 ns ( 62.88 % )
            Info: Total interconnect delay = 1.066 ns ( 37.12 % )
        Info: - Longest clock path from clock "Clk" to source register is 2.872 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'
            Info: 3: + IC(0.927 ns) + CELL(0.666 ns) = 2.872 ns; Loc. = LCFF_X9_Y18_N5; Fanout = 2; REG Node = 'Cout[1]'
            Info: Total cell delay = 1.806 ns ( 62.88 % )
            Info: Total interconnect delay = 1.066 ns ( 37.12 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "Clk" to destination pin "Sev_Seg_Led_Sel_n[0]" through register "Sev_Seg_Led_Sel_n[0]~reg0" is 8.294 ns
    Info: + Longest clock path from clock "Clk" to source register is 2.873 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 25; COMB Node = 'Clk~clkctrl'
        Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.873 ns; Loc. = LCFF_X10_Y18_N1; Fanout = 5; REG Node = 'Sev_Seg_Led_Sel_n[0]~reg0'
        Info: Total cell delay = 1.806 ns ( 62.86 % )
        Info: Total interconnect delay = 1.067 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.117 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y18_N1; Fanout = 5; REG Node = 'Sev_Seg_Led_Sel_n[0]~reg0'
        Info: 2: + IC(1.851 ns) + CELL(3.266 ns) = 5.117 ns; Loc. = PIN_181; Fanout = 0; PIN Node = 'Sev_Seg_Led_Sel_n[0]'
        Info: Total cell delay = 3.266 ns ( 63.83 % )
        Info: Total interconnect delay = 1.851 ns ( 36.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Jul 02 22:08:21 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01