{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 02 22:08:03 2008 " "Info: Processing started: Wed Jul 02 22:08:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Segment2 -c Segment2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Segment2 -c Segment2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Segment2.v 1 1 " "Warning: Using design file Segment2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Segment2 " "Info: Found entity 1: Segment2" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Segment2 " "Info: Elaborating entity \"Segment2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Sev_Seg_Led_Data_n\[7\]~reg0 data_in GND " "Warning (14130): Reduced register \"Sev_Seg_Led_Data_n\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 47 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "Sev_Seg_Led_Data_n\[1\]~reg0 data_in GND " "Warning (14130): Reduced register \"Sev_Seg_Led_Data_n\[1\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 47 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Sev_Seg_Led_Data_n\[0\]~reg0 Sev_Seg_Led_Data_n\[3\]~reg0 " "Info (13350): Duplicate register \"Sev_Seg_Led_Data_n\[0\]~reg0\" merged to single register \"Sev_Seg_Led_Data_n\[3\]~reg0\"" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 47 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Segment2\|Disp_Sel 16 " "Info: State machine \"\|Segment2\|Disp_Sel\" contains 16 states" {  } { { "Segment2.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment2/Segment2/Segment2.v" 25 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0 0}